Browse Prior Art Database

Bus Arbitrator

IP.com Disclosure Number: IPCOM000042128D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

McVey, JM: AUTHOR

Abstract

In a given environment, a plurality of controllers associated with a host processor may need to share the same memory or other resource, or they may communicate with a dedicated register bank which is on a bus common to all the controllers. Each controller, dependent on its priority in a system, must gain access to this bus in a timely and orderly manner. This is accomplished by a device which may be referred to as the bus arbitrator. Fig. 1 shows a typical bus arbitrator diagrammatically in terms of its input/output pins. The bus arbitrator contains standard clock generation logic and requires a single oscillator input to drive this clock generation logic. Fig. 2 shows some typical timing generated by the bus arbitrator which drives control signals to all the controllers on the bus.

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Bus Arbitrator

In a given environment, a plurality of controllers associated with a host processor may need to share the same memory or other resource, or they may communicate with a dedicated register bank which is on a bus common to all the controllers. Each controller, dependent on its priority in a system, must gain access to this bus in a timely and orderly manner. This is accomplished by a device which may be referred to as the bus arbitrator. Fig. 1 shows a typical bus arbitrator diagrammatically in terms of its input/output pins. The bus arbitrator contains standard clock generation logic and requires a single oscillator input to drive this clock generation logic. Fig. 2 shows some typical timing generated by the bus arbitrator which drives control signals to all the controllers on the bus. The controllers respectively drive a group of request lines REQ1-3 to ask for a bus cycle and also drive the memory register lines (MEMREG) 1-3 and read- write lines (R/W) 1-4. This informs the bus arbitrator as to the memory or register and read or write operations. A selected controller will receive the next available bus cycle and receive an acknowledgement (ACK) from the bus arbitrator. At that point the controller may use the bus. This particular bus cycle ends when the acknowledge pen becomes inactive. The other controllers will continue to drive their request to the bus arbitrator unit until they receive an acknowledge. They will then terminate their request and...