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Mechanism to Merge Manufacturing and Engineering Start Up and Debug Activities With Functional LSSD Strings

IP.com Disclosure Number: IPCOM000042132D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+2]

Abstract

This article is related to the use of LSSD (Level Sensitive Scan Design) strings at multiple levels: testing during manufacture, start up by development engineering, and operations in the field. Only one pair of scan data lines per card and one pair of scan data lines per chip are used, whereas any combination of strings can be selected. In particular, in any chip, string 0 can be selected. String 0 is by convention a string with no latch at all. It is just a bypass of scan-in and scan-out lines. Another particular case is the string containing all the latches of the chip. If every chip presents all its latches, then the card string will be the string containing all the latches of the card, that is, the manufacturing string. A card with chips arranged thereon is shown in the drawing.

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Mechanism to Merge Manufacturing and Engineering Start Up and Debug Activities With Functional LSSD Strings

This article is related to the use of LSSD (Level Sensitive Scan Design) strings at multiple levels: testing during manufacture, start up by development engineering, and operations in the field. Only one pair of scan data lines per card and one pair of scan data lines per chip are used, whereas any combination of strings can be selected. In particular, in any chip, string 0 can be selected. String 0 is by convention a string with no latch at all. It is just a bypass of scan-in and scan-out lines. Another particular case is the string containing all the latches of the chip. If every chip presents all its latches, then the card string will be the string containing all the latches of the card, that is, the manufacturing string. A card with chips arranged thereon is shown in the drawing. At least one LSSD latch string S is provided on each chip. Data can be loaded in the chip strings through the scan data-in line. The loading is performed under the control of signals on the LSSD address command bus and the 1 out of n decode circuit which conditions logic circuit LC. Thus, the data are loaded into selected strings depending upon the operations to be performed. The mechanism described here for one card, may be extended to several cards on a board or several boards for a full system.

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