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Verification Method for Parity Check Circuits

IP.com Disclosure Number: IPCOM000042146D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Agoglia, RJ: AUTHOR [+3]

Abstract

This is a technique for verifying that parity check circuits in a processing system are operating correctly. It can be used dynamically during system operation. The illustration depicts a typical personal computer-type processing system comprising a processor 1, read-only storage (ROS) 2, random-access memory (RAM) 3 with associated controller 3a, support logic 4, bus 5 linking all of the foregoing elements for sustaining DMA (Direct Memory Access) operations (shared), hard file 6, and I/O controller 7 linking the file to the RAM storage via controller 3a and bus 5. Controller 7 does not use DMA channel 1 but instead uses DMA channel 2 for normal data transfers as well as for the present verification operation.

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Verification Method for Parity Check Circuits

This is a technique for verifying that parity check circuits in a processing system are operating correctly. It can be used dynamically during system operation. The illustration depicts a typical personal computer-type processing system comprising a processor 1, read-only storage (ROS) 2, random-access memory (RAM) 3 with associated controller 3a, support logic 4, bus 5 linking all of the foregoing elements for sustaining DMA (Direct Memory Access) operations (shared), hard file 6, and I/O controller 7 linking the file to the RAM storage via controller 3a and bus 5. Controller 7 does not use DMA channel 1 but instead uses DMA channel 2 for normal data transfers as well as for the present verification operation. On a special command from processor 1, controller 7 causes data with known bad/even parity to be transferred to controller 3a via channel 8. Parity check circuits in both controllers 7 and 3a are actuated by this data to set error interrupts if they are operating properly. Software in the processing system schedules issuance of the above-mentioned special command and the examination of the (expected) interruption status. If interruptions are posted by both controllers, the system recognizes proper operation of the parity check circuits. If an interruption is posted only by controller 7 or controller 3a, or neither, the system recognizes a malfunction in the parity check path.

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