Browse Prior Art Database

Wait/Hold State Generator for a Processor

IP.com Disclosure Number: IPCOM000042170D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Dierks, MM: AUTHOR [+3]

Abstract

To selectively interface a microprocessor to a slower I/O device, wait and hold states are generated during the microprocessor's I/O cycle. Thus, the slower I/O device gets access to the microprocessor bus by prolonging the microprocessor read and write cycles. The I/O device is also able to release the bus, without interfering with the next address cycle of the microprocessor. The microprocessor can be selectively slowed down to allow necessary communication between it and any slower speed device, including memory. Fig. 1 shows a wait/hold state generator as applied to microprocessor 1 (e.g., an INTEL 8085). Two wait states and one hold state are generated during one microprocessor address latch enable ALE read cycle. The ALE read cycle is expanded from three to six clock cycles in this application.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 1

Wait/Hold State Generator for a Processor

To selectively interface a microprocessor to a slower I/O device, wait and hold states are generated during the microprocessor's I/O cycle. Thus, the slower I/O device gets access to the microprocessor bus by prolonging the microprocessor read and write cycles. The I/O device is also able to release the bus, without interfering with the next address cycle of the microprocessor. The microprocessor can be selectively slowed down to allow necessary communication between it and any slower speed device, including memory. Fig. 1 shows a wait/hold state generator as applied to microprocessor 1 (e.g., an INTEL 8085). Two wait states and one hold state are generated during one microprocessor address latch enable ALE read cycle. The ALE read cycle is expanded from three to six clock cycles in this application. The microprocessor's output signals, address latch enable ALE, read RD*, write WR*, clock CLK, input/output or memory not IO/M*, and state-1 S1, are used as inputs to the wait/hold state generator. The signals HOLD and READY, generated by the wait/hold state generator, are inputs to microprocessor 1. The HOLD signal, output of gate 2, is the Boolean AND of S1 and the output of the hold latch H. RD* and WR* are Boolean ANDed as control signals to a qualification latch Q. Latch Q is set by ALE* and reset by WAIT2. The output of latch Q, CYCCTL, is fed into latch W1 and generates signal WAIT1 on occurrence of clock signal CLK. The Q* output signal of latch W1 is the READY output signal of the wait/hold generator. A wait state is generated when READY is in a logical 0 state. The wait state provides additional time for an I/O device to send or receive data. WAIT1 is clocked into latch W2 by CLK, and forms WAIT...