Browse Prior Art Database

Error Correction System Using "Shadow Memory"

IP.com Disclosure Number: IPCOM000042172D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Basilico, AR: AUTHOR [+2]

Abstract

This article discloses an Error Correction System in which two memory cards are written into simultaneously but are read out separately. This automatically creates a back-up (shadow) copy of memory data which allows for an Error Correction Code (ECC) function to correct errors. The figure illustrates a computer arrangement which includes an engine card and a memory consisting of a plurality of memory cards. The representative memory can address up to 512K bytes of memory in 64K byte increments with each increment being defined as a memory "Volume". The first increment, i.e., Volume 0, may be contained on the engine card and up to 7 additional memory cards can be attached (Volumes 1 to 7). Each memory card is normally personalized to a particular memory address range by its "base-in" bits via board wiring.

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Error Correction System Using "Shadow Memory"

This article discloses an Error Correction System in which two memory cards are written into simultaneously but are read out separately. This automatically creates a back-up (shadow) copy of memory data which allows for an Error Correction Code (ECC) function to correct errors. The figure illustrates a computer arrangement which includes an engine card and a memory consisting of a plurality of memory cards. The representative memory can address up to 512K bytes of memory in 64K byte increments with each increment being defined as a memory "Volume". The first increment, i.e., Volume 0, may be contained on the engine card and up to 7 additional memory cards can be attached (Volumes 1 to 7). Each memory card is normally personalized to a particular memory address range by its "base-in" bits via board wiring. In operation, when a "Read" instruction is executed, each memory card compares its "base-in" bits to the storage address register (SAR) bits to determine if it is selected. If selected, data is read out of the selected volume and a parity check is made. For many applications, a simple parity check scheme, which detects, but does not correct errors, is acceptable. However, an error correction scheme can be provided with no changes required on the engine or memory cards. This is accomplished by connecting the not Read/Write (R/W) line from the engine card to one of the base-in bits in predetermined memory volumes calle...