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Fabrication of Polycide Gated Devices Through the Techniques of Lift-Off and RIE

IP.com Disclosure Number: IPCOM000042177D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Cramer, A: AUTHOR [+2]

Abstract

This article relates generally to semiconductor fabrication processes and more specifically to a semiconductor fabrication process which incorporates lift-off and reactive ion etching (RIE) steps to form polycide gated devices. Fabrication of polycide gates for FET devices is achieved as follows: Referring to Fig. 1, a semiconductor device 1 is shown in an intermediate stage of fabrication. A layer 2 of doped polysilicon is deposited on the surface of a substrate 3. Layer 2 is covered by a layer 4 of photoresist. The latter has an opening 5 formed therein by well-known photolithographic techniques. A refractory metal silicide layer 6 and a layer 7 of silicon are evaporated on the surface of resist layer 4 and on the surface of polysilicon layer 2 exposed by the formation of opening 5 therein.

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Fabrication of Polycide Gated Devices Through the Techniques of Lift-Off and RIE

This article relates generally to semiconductor fabrication processes and more specifically to a semiconductor fabrication process which incorporates lift-off and reactive ion etching (RIE) steps to form polycide gated devices. Fabrication of polycide gates for FET devices is achieved as follows: Referring to Fig. 1, a semiconductor device 1 is shown in an intermediate stage of fabrication. A layer 2 of doped polysilicon is deposited on the surface of a substrate 3. Layer 2 is covered by a layer 4 of photoresist. The latter has an opening 5 formed therein by well-known photolithographic techniques. A refractory metal silicide layer 6 and a layer 7 of silicon are evaporated on the surface of resist layer 4 and on the surface of polysilicon layer 2 exposed by the formation of opening 5 therein. At this point, in a lift-off step, resist layer 4 is dissolved in a suitable solvent (acetone), leaving silicon and silicide layer portions over the desired gate region, as shown in Fig. 2. The structure of Fig. 2 is then subjected to an anistropic RIE step using a portion of the silicon layer as an etch mask in FREON* 12 to remove polysilicon 2, producing the structure of Fig. 3. The exposed silicon etch mask is simultaneously etched during the removal of exposed polysilicon 2 and, as a result, no further steps for the removal of the etch mask are required. Unlike conventional processes which r...