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LSSD Implemented With DCVS Logic

IP.com Disclosure Number: IPCOM000042178D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR

Abstract

Level sensitive scan design (LSSD) logic system, as described in U.S. Patents 3,783,254 and 3,806,891, has served to facilitate testing, analysis, and diagnosis of computer hardwares. In this scheme, the logic states within the processor are sampled in register pairs which are chained together electrically to form a long shift register (S/R) during testing. By examining the serial data flow from the S/R, the status of the processor can be monitored for engineering purposes. The standard block diagram for the LSSD S/R bit is shown in Fig. 1 where the L1-latch is both a test and a storage (or logic) element, and the L2-latch is primarily, but not exclusively, a test element. The circuits for L1 and L2 are shown in Fig. 2 and Fig. 3, respectively.

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LSSD Implemented With DCVS Logic

Level sensitive scan design (LSSD) logic system, as described in U.S. Patents 3,783,254 and 3,806,891, has served to facilitate testing, analysis, and diagnosis of computer hardwares. In this scheme, the logic states within the processor are sampled in register pairs which are chained together electrically to form a long shift register (S/R) during testing. By examining the serial data flow from the S/R, the status of the processor can be monitored for engineering purposes. The standard block diagram for the LSSD S/R bit is shown in Fig. 1 where the L1- latch is both a test and a storage (or logic) element, and the L2-latch is primarily, but not exclusively, a test element. The circuits for L1 and L2 are shown in Fig. 2 and Fig. 3, respectively. The principle of operation is as follows: During normal operation, system-clock C is turned on (C=1, C-=0), and the L1-latch (Fig. 2) will serve as part of the data processing hardware performing logic on processor data D. In testing mode, clock C is turned off, causing L1 to capture the last logic state of the processor. Now L1 is isolated from the rest of the logic to form a half of the S/R bit. Subsequently, shift-clock B for L2 (Fig. 3) is turned on, and the data stored in L1 is transferred to L2 which forms the other half of the S/R bit. Afterwards, shift-clock A for L1 is turned on, loading L1 with scan data I which is the content of the preceding L2 (except for the very first one whose input may be controlled by the user). By alternately pulsing clock A and clock B, the state of the processor, captured just before system-clock C was turned off, is shifted out serially for analysis. When both system-clock C and shift-clock A are turned off, L1 latches its stored data. Similarly, when shift-clock B and system-clock C are both turned off, whatever data is in L2 is latched. During the time when system- clock C is on, both outputs of the L2-latch are precharged high unconditionally, a favorable condition for subsequent conditional discharging. Note also that the dotted rectangle of Fig. 2 may be replaced by a complex multi-variable, differential cascode voltage switch (DCVS) network to greatly enhance the logic power of this L1-latch. The load devices can be implemented in various ways, as shown in Fig. 4. Fig. 5 shows how L1-L2...