Browse Prior Art Database

CMOS Programmable Logic Array

IP.com Disclosure Number: IPCOM000042187D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+2]

Abstract

CMOS technology allows for dense packaging of logic functions using low voltage power supplies and featuring high performance and low power dissipation. This article describes a technique for implementing PLA (programmable logic array) structures in CMOS with various clocking alternatives. Fig. 1 illustrates portions of AND and OR sub-arrays of a PLA structure, and associated CMOS device circuits for performing precharging and validation functions. Fig. 2 illustrates the overlapped timing of validation and precharging operations in this system. Referring to these drawings, the C1 clock function unconditionally precharges the "product term" outputs of the AND array which couple to inputs TD, TE, TF, . . . of the OR array. The C1 clock also precharges the outputs of the OR array at t0 time.

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CMOS Programmable Logic Array

CMOS technology allows for dense packaging of logic functions using low voltage power supplies and featuring high performance and low power dissipation. This article describes a technique for implementing PLA (programmable logic array) structures in CMOS with various clocking alternatives. Fig. 1 illustrates portions of AND and OR sub-arrays of a PLA structure, and associated CMOS device circuits for performing precharging and validation functions. Fig. 2 illustrates the overlapped timing of validation and precharging operations in this system. Referring to these drawings, the C1 clock function unconditionally precharges the "product term" outputs of the AND array which couple to inputs TD, TE, TF, . . . of the OR array. The C1 clock also precharges the outputs of the OR array at t0 time. P channel devices, such as T1 and T3, conduct precharging voltages to respective sub-array components when the C1 clock is low (Fig. 2), charging outputs of both sub-arrays to a +V level. The C1 clock acts through N channel devices T2 to validate/discharge the AND array outputs. The assumption here is that the polysilicon input levels to the AND array from the partitioning logic are valid and stable before the positive transition of the C1 clock, so that product term outputs can be properly validated at the rising edge of the C1 clock. The C2 clock validates outputs of the OR array by allowing N channel devices T4 to conduct while the C2 clock is in its valid (+) phase. If a product term output is active (+), the respective OR array output will discharge through TD, TE,. . . in series with the devices T4. Clock C2 can also be used to gate the OR array outputs into polarity hold latches to store PLA outputs while the OR array...