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Charge-Controlled Memory Cell

IP.com Disclosure Number: IPCOM000042191D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Penoyer, RF: AUTHOR

Abstract

A memory cell, capable of non-destructive read, is provided having signal levels which are not directly dependent on stored charge. The circuit of the cell is illustrated in Fig. 1, and a pulse program which may be used to operate the cell is indicated in Fig. 2. The cell utilizes the state of charge at node N on a storage capacitor C to control the conduction state of field-effect transistor T1. Transistor T2, having a reset pulse R applied to its control gate, is provided to discharge capacitor C during a reset period, indicated in Fig. 2, in preparation for a write operation. If a 0 digit of binary information is to be stored in the cell, a bit/sense line B/S is pulsed to a voltage V prior to applying the voltage V to a word line W.

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Charge-Controlled Memory Cell

A memory cell, capable of non-destructive read, is provided having signal levels which are not directly dependent on stored charge. The circuit of the cell is illustrated in Fig. 1, and a pulse program which may be used to operate the cell is indicated in Fig. 2. The cell utilizes the state of charge at node N on a storage capacitor C to control the conduction state of field-effect transistor T1. Transistor T2, having a reset pulse R applied to its control gate, is provided to discharge capacitor C during a reset period, indicated in Fig. 2, in preparation for a write operation. If a 0 digit of binary information is to be stored in the cell, a bit/sense line B/S is pulsed to a voltage V prior to applying the voltage V to a word line W. Since the voltage V is applied to both sides of capacitor C, no charge is accumulated at node N after voltage V is removed from the word line W and bit/sense line B/S. Thus, zero voltage at node N represents a 0 digit, as indicated in Fig. 2. If a 1 digit of binary information is to be stored, the bit/sense line B/S remains at zero voltage or ground potential when the word line W is pulsed to voltage V. After voltage V is removed from word line W, capacitor C remains charged to voltage V minus voltage VF, which is the voltage drop across diode D1, turning on transistor T1. To read information stored in the cell, word line W is pulsed to a voltage Vr which has a magnitude somewhat smaller than that of v...