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Distributed Logic Low Temperature Circuit

IP.com Disclosure Number: IPCOM000042192D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Davidson, A: AUTHOR [+2]

Abstract

Combining a low-inductance SQUID (Superconducting Quantum Interference Device) with low-capacitance high-current junctions and a multi-turn primary winding, voltage balancing the SQUID below V(min), and using a turn-on current well below Im(0), makes possible a NOR circuit with characteristics appropriate for manufacturable combinatorial logic. All necessary logic circuits for computer operation, including latches, may be implemented in NOR logic. Fig. 1 shows a distributed logic circuit 1 with one input winding 2 of five turns and a DC input winding 3 of one turn. Output 4 is to a 10 L transmission line. To improve noise immunity and design margins, it is recommended that each gate be limited to one Y input winding.

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Distributed Logic Low Temperature Circuit

Combining a low-inductance SQUID (Superconducting Quantum Interference Device) with low-capacitance high-current junctions and a multi-turn primary winding, voltage balancing the SQUID below V(min), and using a turn-on current well below Im(0), makes possible a NOR circuit with characteristics appropriate for manufacturable combinatorial logic. All necessary logic circuits for computer operation, including latches, may be implemented in NOR logic. Fig. 1 shows a distributed logic circuit 1 with one input winding 2 of five turns and a DC input winding 3 of one turn. Output 4 is to a 10 L transmission line. To improve noise immunity and design margins, it is recommended that each gate be limited to one Y input winding. The Y input winding 2 is the multi-turn input winding which might fan out to the other multi-turn input windings. Input X is the DC power input which might be from an external DC bias or another gate. The gate output=X AND (NOT Y). Fig. 2 is an I-V curve for the logic gate. Load line 5 falls well down on the I-V curve because the gate current is kept low. Fig. 3 shows the interferometer threshold curve of I(max) versus I(min). Operating region 6 is just below cutoff point 7. If this circuit were implemented in the form of an interferometer, the threshold curve assumes the form shown in Fig. 3. The interferometer self-inductance is very low, causing the floor of the threshold curve to go to I(gate) = 0. The low inductance interferometer requires less space than the current injection logic (CIL) interferometer; however, the multiple turns consume a significant amount of space (unless more than two wiring levels are used), thus making both total device sizes equal in area. The circuit of this article improves the distributed logic design margins because the multi-turn input winding permits a relatively small current in i...