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High Performance Lateral Bipolar Transistor on Insulating Substrate

IP.com Disclosure Number: IPCOM000042198D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR [+2]

Abstract

This article relates generally to semiconductor devices and fabrication methods therefor and more particularly to the structure of a lateral bipolar transistor on an insulating substrate and its method of fabrication. Fig. 1 shows the structure of an npn lateral transistor 1. Transistor 1 is isolated by an insulator 2 at the bottom and by ROX 3 around its periphery. Insulator 2 is silicon oxide formed on a silicon substrate 4. The material of transistor 1 may be prepared by a zone-melting technique (recrystallization of polysilicon on oxide). Alternatively, the material of transistor 1 may be silicon-on-sapphire. The performance of lateral transistor 1 is enhanced significantly when the Si-layer (epi) on insulator 2 is thin and the base width is narrow. The preferred epi thickness is about 0.5 mm and the WBN0.2N 0.

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High Performance Lateral Bipolar Transistor on Insulating Substrate

This article relates generally to semiconductor devices and fabrication methods therefor and more particularly to the structure of a lateral bipolar transistor on an insulating substrate and its method of fabrication. Fig. 1 shows the structure of an npn lateral transistor 1. Transistor 1 is isolated by an insulator 2 at the bottom and by ROX 3 around its periphery. Insulator 2 is silicon oxide formed on a silicon substrate 4. The material of transistor 1 may be prepared by a zone- melting technique (recrystallization of polysilicon on oxide). Alternatively, the material of transistor 1 may be silicon-on-sapphire. The performance of lateral transistor 1 is enhanced significantly when the Si-layer (epi) on insulator 2 is thin and the base width is narrow. The preferred epi thickness is about 0.5 mm and the WBN0.2N 0.3 mm (or comparable to that of a vertical transistor). As a result, the base resistance and base transit time of transistor 1 is comparable to that of a vertical transistor, and, therefore, the maximum speed of such transistor is also comparable to that of a vertical transistor. The advantage of transistor 1 is that it has very small parasitic capacitance and the emitter and collector capacitances are both smaller than that of a vertical transistor by a factor of 2-3. The current gain is high since there is no parasitic shunt diode between the emitter and base and there is no diffusion capacitance due to base-stretching effect since there is no lightly doped collector region. The circuits built with lateral transistor 1 exhibit lower power-delay product by a factor of 2-3 and have comparable maximum speed. The structure of Fig. 1 may be fabricated using conventional submicron lithography or "spacer" techniques. The below-described steps illustrate a fabrication procedure using a "spacer" technique. Although the procedure is illustrated for an npn transistor, it should be appreciated that pnp transistors can be fabricated using the same steps and opposite dopant conductivity types. Fig. 2 shows the structure of Fig. 1 at an intermediate stage in its fabrication. Fig. 2 shows an epitaxial layer 5 in which lateral transistor 1 is to be formed surrounded by ROX regions 3. Layer 5 is formed by the recrystallization of a layer of polycrystalline silicon using known techniques. Regions 3 and layer 5 are covered by a deposited p+ polycrystalline or polycide layer 6. Alternatively, layer 6 may be deposited without a dopant. Subsequently, it will be doped by ion implantation after the formation of the emitter and collector...