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Process for Deep Dielectric Isolation

IP.com Disclosure Number: IPCOM000042205D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Chicotka, S: AUTHOR [+3]

Abstract

This article relates generally to processes involved in the fabrication of integrated circuits and more particularly to a method for producing deep dielectric isolation for bipolar devices. The conventional method for producing deep dielectric isolation consists of reactive ion etching a trench through an epitaxial layer and subcollector implant. The trench is then filled with oxide or some other material. In the present process, columns of oxide, as shown in Fig. 1, are produced by first growing an oxide on a substrate. In a subsequent photolithographic and etching step, the oxide is patterned and etched by reactive ion etching to provide columns of oxide, as shown in Fig. 1. Fig. 2 shows the structure of Fig.

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Process for Deep Dielectric Isolation

This article relates generally to processes involved in the fabrication of integrated circuits and more particularly to a method for producing deep dielectric isolation for bipolar devices. The conventional method for producing deep dielectric isolation consists of reactive ion etching a trench through an epitaxial layer and subcollector implant. The trench is then filled with oxide or some other material. In the present process, columns of oxide, as shown in Fig. 1, are produced by first growing an oxide on a substrate. In a subsequent photolithographic and etching step, the oxide is patterned and etched by reactive ion etching to provide columns of oxide, as shown in Fig. 1. Fig. 2 shows the structure of Fig. 1 after an epitaxial layer of semiconductor has been grown in the regions between the oxide columns using a well-known process which selectively deposits on the semiconductor region and not on the oxide columns. This layer is characterized as the subcollector layer after it is ion implanted with an appropriate dopant. Fig. 3 shows the structure of Fig. 2 after a second epitaxial semiconductor layer has been deposited. The semiconductor regions thus formed are those in which the active devices are formed. In a final step, the surface of the structure is planarized in a well-known manner.

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