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Fast ALU Path and Reduction of Microcycles for Multiple Word Addition

IP.com Disclosure Number: IPCOM000042211D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

del Sol, PD: AUTHOR [+4]

Abstract

A critical timing path through an Arithmetic Logic Unit (ALU) is resolved. In a representative Emulator, the path for an ALU operation may be critical. To meet a 100 nsec cycle, for example, special design considerations need to be implemented. In some existing processors, such as the IBM Series/1 processor, multiple sources are funneled on to a single ALU input (Fig. 1). In order to meet the timings through the critical path, the external funnel is removed and the sources are incorporated into a wide ALU input (Fig. 2). Fig. 3 shows hardware logic used for funneling multiple sources into the ALU. Fig. 4 shows hardware logic for ALU input without the external funnel. The latter method requires more logic, but it has one less delay level in the ALU path.

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Fast ALU Path and Reduction of Microcycles for Multiple Word Addition

A critical timing path through an Arithmetic Logic Unit (ALU) is resolved. In a representative Emulator, the path for an ALU operation may be critical. To meet a 100 nsec cycle, for example, special design considerations need to be implemented. In some existing processors, such as the IBM Series/1 processor, multiple sources are funneled on to a single ALU input (Fig. 1). In order to meet the timings through the critical path, the external funnel is removed and the sources are incorporated into a wide ALU input (Fig. 2). Fig. 3 shows hardware logic used for funneling multiple sources into the ALU. Fig. 4 shows hardware logic for ALU input without the external funnel. The latter method requires more logic, but it has one less delay level in the ALU path. In addition to decreasing the delay through the ALU path, it is possible to save microcycles while executing multiple word addition. In a standard ALU, a multiple word addition operation requires an extra cycle after each word addition (A+B) to perform an (A+Carry). In the representative Emulator, the extra cycles can be saved by doing (A+B+Carry) in the same microcycle. This is accomplished by storing the carry output from the ALU as a result of an addition (A+B) in carry latch block 1 (Fig.
5). This is used as the carry input 2 to the ALU for the next addition (A+B+Carry). Therefore, when the ALU controls decode an A+B+Carry operation, the ALU...