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Test Pattern Generation Methodology for LSI/VLSI Module Level Testing and In-Circuit Card Level Testing

IP.com Disclosure Number: IPCOM000042218D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Dinwiddie, JM: AUTHOR [+2]

Abstract

A test pattern methodology is described that eliminates manual data entry normally required to generate numerous test patterns for testing LSI/VLSI components in a high speed test system(s). Here, a basic interpreter is used to generate circuit card level commands. This causes and/or generates complex I/O channel signals (activities). A single basic statement generates thousands of input stimuli which are captured, stored and forwarded to a data set via a logic analyzer. Logic analyzers are capable of sampling digital information at very high rates and transmitting the sample data into a host data set.

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Test Pattern Generation Methodology for LSI/VLSI Module Level Testing and In-Circuit Card Level Testing

A test pattern methodology is described that eliminates manual data entry normally required to generate numerous test patterns for testing LSI/VLSI components in a high speed test system(s). Here, a basic interpreter is used to generate circuit card level commands. This causes and/or generates complex I/O channel signals (activities). A single basic statement generates thousands of input stimuli which are captured, stored and forwarded to a data set via a logic analyzer. Logic analyzers are capable of sampling digital information at very high rates and transmitting the sample data into a host data set. Once the data set is created, a conversion program is run or executed to either format the data to develop patterns for a module level test system or for data entry into an Engineering Design System (EDS) for final development of manufacturing engineering test patterns for card level testing. Such systems are then used for card test. This methodology can be used for generating the test patterns for in- circuit testing and/or functional testing of fully populated cards. In addition, many hours of manual data entry for generating test patterns for vendored LSI/VLSI semiconductor products is effectively eliminated. An important aspect of the methodology is that the device at the module level is tested using the same input stimulus that the device will "see" at syste...