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Browse Prior Art Database

Pseudo Port for a Communications Subsystem

IP.com Disclosure Number: IPCOM000042219D
Original Publication Date: 1984-Apr-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Cianciosi, MN: AUTHOR [+2]

Abstract

Outboard processors that are utilized as multiplexers and connected by a common bus usually require a different hardware interface between the processors and the interface to the port or channel of the host system. This article describes a communication subsystem in a host system which utilizes microprocessors as outboard processors in which the handshaking mechanism normally done by the port-side hardware is emulated in the microcode of the outboard processors. The communication subsystem attachment supports three interfaces. The processor interface 12 communicates with the microprocessor, the device interface 11 provides the BSC/SDLC line adapter access to the microprocessor and the Port/Pseudo Port 15 assures commonality to the host system control store processor and any of the microprocessors that are cascaded.

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Pseudo Port for a Communications Subsystem

Outboard processors that are utilized as multiplexers and connected by a common bus usually require a different hardware interface between the processors and the interface to the port or channel of the host system. This article describes a communication subsystem in a host system which utilizes microprocessors as outboard processors in which the handshaking mechanism normally done by the port-side hardware is emulated in the microcode of the outboard processors. The communication subsystem attachment supports three interfaces. The processor interface 12 communicates with the microprocessor, the device interface 11 provides the BSC/SDLC line adapter access to the microprocessor and the Port/Pseudo Port 15 assures commonality to the host system control store processor and any of the microprocessors that are cascaded. The two microprocessor attachments shown in Fig. 1 can be considered as a local processor 1 and as a remote processor 9. The local processor 1 provides controls via microcode to allow one or more remote processors to communicate directly with the host system port. The microcode in the local processor 1 simulates the host system port's hardware where applicable when communicating with the remote processor 9 over the Pseudo Port 15. Buffer 5 is a byte register that accepts the data on the Data Bus Out of the port interface. This data can be the result of a cycle steal outbound operation from host system storage or I/O load commands. From here the data can be passed either to the microprocessor storage via funnel 7 or to the remote processor, in the case of cycle stealing, via funnel 8 to load its buffer 14. The remote processor 9 can then direct the data to its microprocessor. Going in the other direction, buffer 3 and buffer 4 of the local processor 1 are byte registers that connect to the host system port via funnel 2. The data is placed in these registers under microprogram control, and the port hardware interface determines which buffer is funneled to the host system upon detection of an I/O Sense command or a cycle steal inbound operation. Funnel 2 is the inbound bus or Data Bus In to the host system port 13. The remote processor 9 performs the same type of functi...