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Digital Data Separator With Memory

IP.com Disclosure Number: IPCOM000042229D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Frazier, GR: AUTHOR [+2]

Abstract

The inclusion of a memory in a data separator circuit for distinguishing between data pulses and clock pulses on a magnetic recording allows transitions of the data window signal to be based not only on the presently read pulse, but also on a weighted average of past pulses. Magnetic recording systems require a data separator which distinguishes between read-back pulses as either data pulses or clock pulses. This is accomplished by supplying a data window (DW) signal which is at an up level during data pulses and at a down level during clock pulses. Existing digital data separators base each data window signal transition on the presently read pulse only, thereby ignoring all previous pulses.

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Digital Data Separator With Memory

The inclusion of a memory in a data separator circuit for distinguishing between data pulses and clock pulses on a magnetic recording allows transitions of the data window signal to be based not only on the presently read pulse, but also on a weighted average of past pulses. Magnetic recording systems require a data separator which distinguishes between read-back pulses as either data pulses or clock pulses. This is accomplished by supplying a data window (DW) signal which is at an up level during data pulses and at a down level during clock pulses. Existing digital data separators base each data window signal transition on the presently read pulse only, thereby ignoring all previous pulses. This insensitivity to all past history causes these data separators to be adversely affected by short-term inaccuracies of the read-back pulses, such as bit shifts. In Fig. 1, a SHORTEN pulse is output from the UP/DOWN counter each time the counter reaches a count of N. A LENGTHEN pulse is output by the counter each time the counter reaches a count of -N. In the absence of SHORTEN or LENGTHEN pulses, the controlled divider divides the CLOCK input (frequency Af) into the DW output frequency f. Pulses on the SHORTEN input of the divider, however, instantaneously raise the frequency of its output by shortening a single up or down level of its output. Likewise, pulses on the LENGTHEN input to the controlled divider instantaneously lower its output frequency by lengthening a single up or down level of its output. In addition to the divided signal outputs, the controlled divider controls a NOMINAL signal line which is active whenever the last read pulse occurred in a small region centered between successive transitions of DW. Fig. 2 shows the relationship of these and other signals for a typical modified frequency modulation data pattern, although, this technique is applicable to all run-length-limited encoding methods without further modification. The controlled divider divides the CLOCK signal into signals DW (at frequency f) and EARLY/LATE (E/L at frequency 2f). The file readback pulse (RP) then latches the value of E/L into the D flip-flop, providing the UP/DOWN (U/D) signal for the counter. The counter then counts up or down upon each rising edge of DW...