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Real-Time Laplacian Image Edge Detector on a Single Vlsi Chip

IP.com Disclosure Number: IPCOM000042234D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 4 page(s) / 21K

Publishing Venue

IBM

Related People

Anastassiou, D: AUTHOR [+2]

Abstract

This publication describes a single chip Laplacian image edge detector which can perform the Laplacian operation A0 - 1/8*(A1+A2+...+A8) on every picture element (pixel) of a 512x512 digital image in real time. The chip consists of an array MxN of processing elements (PEs) which operate in parallel. A picture is divided into regions of MxN pixels which are loaded into the chip from the picture buffer via multiple serial paths. The pixels are distributed throughout the chip so that each PE receives one pixel. The PEs consist roughly of a single-bit adder, two shift registers, two multiplexers, nine tri-state buffers to control near-neighbor communication, a latch and other control logic, as seen in Fig. 1.

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Real-Time Laplacian Image Edge Detector on a Single Vlsi Chip

This publication describes a single chip Laplacian image edge detector which can perform the Laplacian operation A0 - 1/8*(A1+A2+...+A8) on every picture element (pixel) of a 512x512 digital image in real time. The chip consists of an array MxN of processing elements (PEs) which operate in parallel. A picture is divided into regions of MxN pixels which are loaded into the chip from the picture buffer via multiple serial paths. The pixels are distributed throughout the chip so that each PE receives one pixel. The PEs consist roughly of a single-bit adder, two shift registers, two multiplexers, nine tri-state buffers to control near-neighbor communication, a latch and other control logic, as seen in Fig. 1. A PE communicates with its eight neighbors via serial paths and performs all additions and other operations required by the enhancement process on a bit-by-bit basis. Upon completion of the enhancement of the on-chip picture region, the processed data is unloaded from the chip and another picture region is loaded in. This sequence is repeated until the entire picture is enhanced. Key features of the chip are the following: a) The 8-neighbor interconnection scheme is reduced to a 4-neighbor interconnection scheme by exploiting the structured nature of inter-PE communications and providing signal isolation through the tri-state buffers. b) The loading and unloading of data occur via the two shift registers SR_IN and SR_OUT which, connected together with the corresponding registers of the PEs at the same column, behave as if they are two long shift registers for data input and output. During the actual processing, the shift register at the output of the adder (SR_OUT) is constantly operating and storing the intermediate results while the other shift register (SR_IN) is also constantly operating performing circular shifting and providing data to the neighboring PEs. Therefore, these shift registers can be readily implemented as a series of inverters separated by pass transistors. The gates of the pass transistors must be connected to two nonoverlapping clock phases. These considerations, together with the other pipelining and parallelism features described in this article, make the overall chip design approach to be that of a "systolic array." For the implementation proposed here, it is assumed that only the edge detection must be done in 33 msecs, for real time operation, and found that execution speed was not difficult to be met. The main emphasis was to maximize the number of PEs per chip, and for this purpose implementations with a smaller number of devices are preferred, sometimes at the expense of additional gate delays. A clock rate of 10 MHz is assumed for data loading/unloading per I/O pin and also 10 Mops for speed of algorithm execution (assuming an operation is defined as the equivalent of a one-bit addition). We assigned 32 pins for pixel data loading/unloadin...