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Transparent Mode in an I/O Controller

IP.com Disclosure Number: IPCOM000042236D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Beukema, BL: AUTHOR [+3]

Abstract

In large and medium-performance systems (Fig. 1) communication between an I/O device 300 and the system CPU 100 is controlled by an I/O controller 200. Nominally, this architecture enhances the total performance of the system. However, to establish basic communication between an I/O device and the system CPU, all three units must be operational. It is desirable to reduce the number of functional levels required to establish basic communication, for example, during temporary errors and permanent failures. I/O controller 200 contains an I/O microprocessor 210, I/O read/ write storage 220, and bus coupler 230.

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Transparent Mode in an I/O Controller

In large and medium-performance systems (Fig. 1) communication between an I/O device 300 and the system CPU 100 is controlled by an I/O controller 200. Nominally, this architecture enhances the total performance of the system. However, to establish basic communication between an I/O device and the system CPU, all three units must be operational. It is desirable to reduce the number of functional levels required to establish basic communication, for example, during temporary errors and permanent failures. I/O controller 200 contains an I/O microprocessor 210, I/O read/ write storage 220, and bus coupler 230. In normal mode, the bus coupler handles and synchronizes I/O commands issued from the system CPU and from the I/O microprocessor, generates interrupt requests to either processor, and manages data transfer via cycle steals between the two processors. For special periods of operation, the bus coupler may also be operated in a transparent mode. While in transparent mode, the I/O microprocessor and the I/O storage are disabled and the system channel 110 is coupled directly to the I/O bus 310. This allows the system CPU to communicate directly with the I/O adapters. While in transparent mode, the bus coupler allows all forms of communication between the system CPU and the I/O adapter. These include I/O instructions, cycle-steal data transfer, and interrupts. Device addressing in transparent mode is controlled by the bus coupler. That is, when the system CPU issues an I/O command to an I/O adapter in transparent mode, the system CPU issues the command to the device address of the bus coupler, not to the device address of the I/O adapter. Logic and registers in the bus coupler transpose its device address to the device address of the desired I/O adapter on the I/O channel. Fig. 2 shows how this transposition operates. Prior to setting transparent mode latch 232, the system CPU loads the device address of the I/O adapter to which an I/O command will be issued into device address buffer 231 in the bus coupler. Latch 232 is then set by issuing an I/O command from the system CPU to the bus coupler.

The bus coupler will continue to detect its assigned device address on the system channel using comparator 233; however, when a bus-coupler device- address hit occurs and the device-selected latch 234 is set, the system channel DBO (in this application, DBO bits 0-3 contain the device address) is inhibited by AND gate 235, and buffer 231 is gated onto the I/O channel outbound data lines by AND gate 236 before the command is passed to the I/O channel. Therefore, the I/O adapter will be presented with its device address on the I/O channel.

The I/O adapter will then execute the I/O command as usual. This design allows I/O commands issued by the system C...