Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Device-Level Control BUS for I/O Devices in a DATA Processor

IP.com Disclosure Number: IPCOM000042238D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Burns, CS: AUTHOR [+6]

Abstract

A device-level control (DLC) bus transfers byte-multiplexed data between multiple input/output (I/O) devices and a buffer. Some DLC bus lines are common to all devices, while others are replicated for each device. High-speed byte multiplexing allows efficient mixing of I/O devices having varying data rates on the same bus. Processing engine 10 (Fig. 1) interfaces to a burst-multiplexed system channel of the type described in U.S. Patent 4,077,060. Multiple-buffer file adapter (BFA) 30 has a channel interface 31 for transferring a multi-byte block of data in a single burst to/from one of a number of first-in/first-out (FIFO) buffers 32, each holding at least a whole block of bytes. DLC interface 33 transfers interleaved single data bytes between all the buffers and multiple I/O devices 40 simultaneously.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 42% of the total text.

Page 1 of 2

Device-Level Control BUS for I/O Devices in a DATA Processor

A device-level control (DLC) bus transfers byte-multiplexed data between multiple input/output (I/O) devices and a buffer. Some DLC bus lines are common to all devices, while others are replicated for each device. High-speed byte multiplexing allows efficient mixing of I/O devices having varying data rates on the same bus. Processing engine 10 (Fig. 1) interfaces to a burst-multiplexed system channel of the type described in U.S. Patent 4,077,060. Multiple-buffer file adapter (BFA) 30 has a channel interface 31 for transferring a multi-byte block of data in a single burst to/from one of a number of first-in/first-out (FIFO) buffers 32, each holding at least a whole block of bytes. DLC interface 33 transfers interleaved single data bytes between all the buffers and multiple I/O devices 40 simultaneously. MBA 50 can also transfer I/O-command (direct program control (DPC)) bytes directly from channel interface 31 to DLC interface 33, without any buffer delay. DLC bus mediates the byte-multiplexed transfer of data between multiple I/O devices 40 and multiple FIFO buffers 32 simultaneously. The DLC bus has common lines 51 paralleled to every device 40, and individual lines 52, for which the DLC interface provides a separate set for each device. The common 9-line DATA BUS is bidirectional and is used to transfer direct program control (DPC) and direct memory access (DMA; sometimes called cycle-steal) data between the device adapters and the BFA. The BFA maintains odd parity for both DMA and DPC write operations, and checks for odd parity on DMA and DPC read operations. The common 5-line ADDRESS BUS provides addressability to the internal register space of the DLCs during DPC cycles. TRANSFER READY is used by the BFA to indicate to each of the devices when the BFA is ready to transfer or receive data. There is one TRANSFER READY for each device. At the start of an operation the device must wait for this line to come active before requesting DMA data cycles. If the line becomes inactive, transfer halts and the device should generate an interrupt. During DPC cycles, COMPONENT SELECT is used by the BFA to indicate that a handshake sequence is in progress. It also provides timing for the DPC data. If the cycle is a DPC read, the device should place data on the bus for the duration of COMPONENT SELECT. If the cycle is a DPC write, the BFA will place data on the bus for the duration of COMPONENT SELECT. There is one COMPONENT SELECT for each DLC. The devices raise DMA REQUEST to indicate that a byte of DMA data is to be transferred. The BFA activates DMA ACKNOWLEDGE in response to this line. There is one DMA REQUEST line for each device. DMA ACKNOWLEDGE indicates to the device that a DMA cycle is in progress. It also provides timing for the DMA data. If the cycle is a DMA read, the device should place data on the bus for the duration of DMA ACKNOWLEDGE. If the cycle is a DMA write, t...