Browse Prior Art Database

Method for saving masks through metal and via programmability

IP.com Disclosure Number: IPCOM000042246D
Publication Date: 2005-Feb-03
Document File: 2 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for saving masks through metal and via programmability. Benefits include improved functionality and improved performance

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Method for saving masks through metal and via programmability

Disclosed is a method for saving masks through metal and via programmability. Benefits include improved functionality and improved performance.

Background

              After a product is taped-out, bugs may be found by silicon debug or other methods. These bug findings may result in a change to a subset of masks layers from metal1 (M1) to metal6 (M6) and/or via1 to via5. As a result, the chip revision ID must change. If the layers required to change the revision ID are not the same as for the design release, a new mask must be manufactured for the chip revision. The extra mask increases the cost. Mask costs have soared over 40% from generation to generation and are expected to continue.

General description

              The disclosed method includes changing any net connection to another connection by specifying any one layer between M1-M6 or via1-via5. The method applies to any metal layer process.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to saving metal mask layers in any net where a selectable mux is required
•             Improved performance due to providing a programmable 2-to-1 multiplex (mux) where the input-to-output path is selectable by the addition and deletion of any one metal or via layer

Detailed description

              The disclosed method includes changing any net connection to another connection by specifying any 1-layer between M1-M6 or via1-via5. For example, bit[0] of a chip’s revision ID should be logic 0 (VSS, see Figure 1). After the via2 mask layer is changed, the chip revision bit[0] must change to logic 1 (VCC). Input1 is tied to VSS. Input2 is tied to VCC. Output is tied to the chip revision bit[0] for the original tapeout. All the metal and vias on the left...