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Method for lithography-free production of pedestals for replacement metal gate integration with a physical gate length of 12 nm or less

IP.com Disclosure Number: IPCOM000042255D
Publication Date: 2005-Feb-03
Document File: 2 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for lithography-free production of pedestals for replacement metal gate integration with a physical gate length of 12 nm or less. Benefits include improved functionality.

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Method for lithography-free production of pedestals for replacement metal gate integration with a physical gate length of 12 nm or less

Disclosed is a method for lithography-free production of pedestals for replacement metal gate integration with a physical gate length of 12 nm or less. Benefits include improved functionality.

Background

              Carbon nanotubes are robust materials. They withstand typical dry etch plasma conditions, which makes them candidates for erosion-free hardmasks. The tubes can be easily isolated by like and small dimensions. Features can be formed around 12-nm or smaller sizes. This size is beyond the limits of the lithographic process. As a result, a method is required to incorporate metal gates and high dielectric constant (k) gate dielectrics into ultra small transistors.

Description

              The disclosed method uses of single-walled carbon nanotubes (~2-12 nm) as hardmask layers for etching ultrafine features to dimensions much smaller than possible by lithography.

              For example, a substrate can be patterned to form place-holder gate electrodes that are ultimately be replaced by the atomic layer deposition (ALD) of high-k and metal gates. The pedestal material  is typically polysilicon or silicon nitride. The pedestal material layer is dry etched to form the pedestals. The nanotubes are removed and the conventional replacement gate process continues (see Figure 1).

              The disclosed method can be extended to use larger mul...