Browse Prior Art Database

Universal Physical Memory Bit Fail Map

IP.com Disclosure Number: IPCOM000042285D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Kurth, RF: AUTHOR [+2]

Abstract

In the conduction of failure analysis it is frequently convenient to organize information about a memory array such that it corresponds to the geometric layout of the array. Information about failure modes and mechanisms is easily obtained from such a geometric display of failure data. (For example, poor sense amp performance is often indicated by failures on the edges of an array.) The problem of how to conveniently map the failed locations on a memory chip product into a representation which can be displayed on a CRT display, for a multiplicity of memory products to be tested, is solved by the universal physical memory bit fail map invention disclosed as follows. Fig. 1 shows the layout of an exemplary memory.

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Universal Physical Memory Bit Fail Map

In the conduction of failure analysis it is frequently convenient to organize information about a memory array such that it corresponds to the geometric layout of the array. Information about failure modes and mechanisms is easily obtained from such a geometric display of failure data. (For example, poor sense amp performance is often indicated by failures on the edges of an array.) The problem of how to conveniently map the failed locations on a memory chip product into a representation which can be displayed on a CRT display, for a multiplicity of memory products to be tested, is solved by the universal physical memory bit fail map invention disclosed as follows. Fig. 1 shows the layout of an exemplary memory. Examination of the word decoder will illustrate that the arrangement of the word lines does not follow a sequential order of monotonic increase. That problem is overcome by using personalized address generators for testing each product. Unusual wiring patterns occurring at the module level can similarly be taken into account. Fig. 2 illustrates the universal physical memory bit fail map circuit. An 8 MHz oscillator 2 has an output connected to a video control circuit 4. The video control circuit 4 provides a combined video output signal, horizontal sync signal and vertical sync signal, which are input to one input of the two-input AND gate 6. The other input to the AND gate 6 is connected to the single data output of the screen buffer RAM (random-access memory) 8. The output 10 of the AND gate 6 is connected to the input of the video CRT monitor at a point before the horizontal sync signal and vertical sync signal are stripped off the composite signal, leaving the video output signal to be input to the CRT grid itself. In this manner, the oscillator 2 and video control 4 will generate the rastor for the CRT display. Stage 1 - Storing Error Data in the Screen Buffer RAM The tester 12 tests the memory device 13 by sequentially incrementing the address input to the memory device under test, and reading out a previously stored pattern of data. These test results can either be stored for later analysis, or can be output in real time. For this example, as the tester 12 sequentially increments the address to the device under test 13, the address is also output on line 14 through the multiplexer 16 to the address input 17 of the screen buffer RAM 8. When the 16-bit address output from the tester 12 on line 14 achieves an all ones state, the counter 18, connected to the line 14, is incremented by unity. This four-bit counter 18 outputs its count value as one input through the multiplexer 20 to a high order address input 21 of the screen buffer RAM 8. When the counter 18 reaches an all zeros state, an output A serves to reset a timer 28, thereby disabling the write enable input through line 29 and gate 30, to the screen buffer RAM 8, and also switching the state of the multiplexer 16. During th...