Browse Prior Art Database

P and N Collar CMOS Technology

IP.com Disclosure Number: IPCOM000042294D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Gaensslen, FH: AUTHOR [+2]

Abstract

This article relates generally to CMOS (complementary metal-oxide-semiconductor) devices and processes and more specifically to such devices and a process for their fabrication wherein the sources and drains of the devices are surrounded by collars of opposite conductivity type. Conventional CMOS technology tends to be a high mask count processing sequence due to the necessity of complementary MOS transistors on the same semiconductor chip. This article describes a key simplification to the CMOS process sequence which will result in lower processing costs. Complementary MOS transistors are implemented by using appropriately doped collars surrounding the MOS source and drain in a fashion similar to a DMOS device [1]. The nMOS transistor employs a p-doped collar; the pMOS transistor employs an n-doped collar.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 1

P and N Collar CMOS Technology

This article relates generally to CMOS (complementary metal-oxide- semiconductor) devices and processes and more specifically to such devices and a process for their fabrication wherein the sources and drains of the devices are surrounded by collars of opposite conductivity type. Conventional CMOS technology tends to be a high mask count processing sequence due to the necessity of complementary MOS transistors on the same semiconductor chip. This article describes a key simplification to the CMOS process sequence which will result in lower processing costs. Complementary MOS transistors are implemented by using appropriately doped collars surrounding the MOS source and drain in a fashion similar to a DMOS device [1]. The nMOS transistor employs a p-doped collar; the pMOS transistor employs an n-doped collar. These collars are formed within a highly resistive (n, f, or i) starting material through the same oxide opening as the respective sources and drains. A sample cross-section of two complementary MOS transistors (such as would be used to realize an inverter) fabricated using the p and n collar technology proposed is shown in the figure. Two distances are important in device design (shown on nMOS only): L, the metallurgical MOS channel length, and L1, the collar separation. The MOS threshold is determined by the collar doping and gate work function for L1 below a critical value; hence, the choice of L1 can be made, as appropriate, independent of device thresholds. The simplified process sequence consist...