Browse Prior Art Database

High Performance Complementary Technology

IP.com Disclosure Number: IPCOM000042296D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Gaensslen, FH: AUTHOR [+2]

Abstract

This article relates generally to high performance CMOS (complementary metal-oxide-semiconductor) devices and more specifically to such devices having a merged or common drain configuration. Conventional bulk CMOS technology suffers from two serious handicaps which limit packing density and performance. First, the inability to consolidate the drain regions and necessary contacts of the complementary load and driver transistors increases the output load and limits packing density, and hence performance. Second, MOS transistor breakdown voltage limitations usually preclude the exploitation of high performance obtainable with high voltage drive levels. The CMOS technology of this article combines increased packing density and high voltage operation to overcome the above-mentioned performance limitations.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 2

High Performance Complementary Technology

This article relates generally to high performance CMOS (complementary metal- oxide-semiconductor) devices and more specifically to such devices having a merged or common drain configuration. Conventional bulk CMOS technology suffers from two serious handicaps which limit packing density and performance. First, the inability to consolidate the drain regions and necessary contacts of the complementary load and driver transistors increases the output load and limits packing density, and hence performance. Second, MOS transistor breakdown voltage limitations usually preclude the exploitation of high performance obtainable with high voltage drive levels. The CMOS technology of this article combines increased packing density and high voltage operation to overcome the above-mentioned performance limitations. Ease of fabrication and latch-up susceptibility are not sacrificed when compared to conventional bulk CMOS technology. A single Schottky barrier contact is used as a self-polarized replacement for both the conventional nMOS and pMOS drain regions, as shown in the figure. Ideally, this Schottky contact should have a barrier height db=0.5(Eg/q) volts to enable symmetric communication with both induced n- and p-channel layers at the surface. The merged drain configuration reduces the output load and enhances packing density, thereby improving performance. In addition, a novel complementary MOS transistor configuration is provided which permits high voltage operation. The individual transistors resemble in part either DMOS [1] or Schottky Barrier FETs [2]. The use of a high resistivity starting material (n, f, or i) sharply lowers the capacitive loading on the output node D of the above figure. In spite of the high resistivity, substrate device punchthrough is not experienced due to the doped collars C surrounding the sources. Note that the structure implements the inverter function with SN set to ground and SP set to VDD . The input (IN) is formed by GN and GP; the merged drain D acts as the output (OUT). Three distances important for device design are shown on the nMOS side only: Lh, the high doped channel length, L1, the low doped channel length, and Lg, the poly-Schottky gap length. The device threshold voltage is determined by the doping level of the Lh region and its physical length, the poly gate work function, and, as usual, tox and Qox . Dimension (L1 + Lg) sets the breakdown voltage of the device. Dimension Lg is unimportant below a critical value; inversion channel communicat...