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Process for Making N-Well Regions Self-Aligned to Field Regions in CMOS

IP.com Disclosure Number: IPCOM000042307D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bakeman, PE: AUTHOR [+2]

Abstract

A process is provided for forming N-well regions for CMOS structures which are self-aligned to field isolation regions. The process is described with reference to Figs. 1-4. On a silicon substrate 12 having a P+ type of conductivity, a P-type region 10 is formed adjacent one of its major surfaces. Dielectric layers 14 and 16, made of SiO2 and Si3N4, respectively, are formed on a surface of P-layer 10. In one example of this process, the SiO2 layer 14 had a thickness of 40 nm and the Si3N4 layer 16 a thickness of approximately 105 nm. The Si3N4 layer 16 is covered by a pyrolytic SiO2 layer 18 which may have a thickness between 200 and 250 nm. The pyrolytic oxide 18 may have a phosphorus concentration of 1 to 2 M% to reduce the stresses on the layer.

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Process for Making N-Well Regions Self-Aligned to Field Regions in CMOS

A process is provided for forming N-well regions for CMOS structures which are self-aligned to field isolation regions. The process is described with reference to Figs. 1-4. On a silicon substrate 12 having a P+ type of conductivity, a P-type region 10 is formed adjacent one of its major surfaces. Dielectric layers 14 and 16, made of SiO2 and Si3N4, respectively, are formed on a surface of P-layer 10. In one example of this process, the SiO2 layer 14 had a thickness of 40 nm and the Si3N4 layer 16 a thickness of approximately 105 nm. The Si3N4 layer 16 is covered by a pyrolytic SiO2 layer 18 which may have a thickness between 200 and 250 nm. The pyrolytic oxide 18 may have a phosphorus concentration of 1 to 2 M% to reduce the stresses on the layer. Following an anneal cycle, a masking layer 20 is formed and patterned on pyrolytic oxide layer 18. The exposed portion of the layer 18 is etched, using conventional wet or dry (or both) etching techniques, stopping inside the pad oxide layer 14 or at the Si surface adjacent layer 14 (Fig. 1). The photoresist (PR) layer 20 is then removed, and the structure is oxidized at about 950OEC in a steam and HCl environment, growing an additional pad oxide having a thickness between 60 and 80 nm. (An alternative step for growing such a pad oxide is to heat the structure at about 1000 to 1025OEC in a dry O2 and HCl ambient.) The thickness of the new pad oxide 14' will be in the range of...