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Cross-Interrogate Directory for a Real, Virtual or Combined Real/Virtual Cache

IP.com Disclosure Number: IPCOM000042312D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR

Abstract

This article describes a logical address (LA) field provided with each entry in a cross-interrogate (XI) directory for each cache directory in a multiprocessor (MP) system in which each CPU has a store-in-cache. Whenever a CPU or channel references main storage, a cross-interrogate XI function is performed in a system control element (SCE) of the MP which contains XI directories for all CPUs connected to the SCE. The XI function determines if the "latest copy" of the addressed data is in a CPU cache or in main storage. In processor cache organizations, it is sometimes desirable to increase substantially the size of the cache, and to structure the storage into hierarchical levels. Furthermore, it is often desirable to address the CPU cache directory with the "logical" form of the address.

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Cross-Interrogate Directory for a Real, Virtual or Combined Real/Virtual Cache

This article describes a logical address (LA) field provided with each entry in a cross-interrogate (XI) directory for each cache directory in a multiprocessor (MP) system in which each CPU has a store-in-cache. Whenever a CPU or channel references main storage, a cross-interrogate XI function is performed in a system control element (SCE) of the MP which contains XI directories for all CPUs connected to the SCE. The XI function determines if the "latest copy" of the addressed data is in a CPU cache or in main storage. In processor cache organizations, it is sometimes desirable to increase substantially the size of the cache, and to structure the storage into hierarchical levels. Furthermore, it is often desirable to address the CPU cache directory with the "logical" form of the address. The logical address may be formed from a base which is a real address or a virtual address. For such an operation, the XI operation described above would be ineffective. Although the XI function (based on AA search) would indicate whether the requested data is in a cache at the logical address position, there would be no convenient way to determine if the requested data is in the cache at another (synonym) position. This is due primarily to the very large number of possible synonym locations for requested data in the cache. The figure illustrates a modified XI directory that solves the synonym problem. Each cache array may be N-way set associative (A,B,C,...), and one such array is provided for each CPU. XI requests are presented to a XI request control block, which sequences the AA entries in an absolute address register (AAR). The AAR provides address and control information to the XI array, as indicated. The compare function is executed on the AA field for all set-associative fields (not shown) in parallel. A compare equal condition in...