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Reduced Logic for Boolean Operations on Raster Display Refresh Buffers

IP.com Disclosure Number: IPCOM000042344D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Bowater, RJ: AUTHOR [+4]

Abstract

Raster graphics displays commonly employ a refresh buffer, a large RAM (random-access memory) storage comprising one or more frame buffers. Each frame buffer consists of a rectangular array of bitlists, one bitlist per separately illuminable point (pixel) on the display screen. These bitlists or lists of bits each represent a greyscale or color index, an index into a video lookup table. This article describes a mechanism whereby the hardware logic associated with changing the contents of frame buffers is reduced, saving card space (real-estate) and cost. This becomes particularly important in the case of a very high performance design which: (a) Provides the full set of sixteen boolean operators: Bitlist-NEW < -- Bitlist-OLD boolop Current-Color (b) Provides for flexible assignment of the RAM storage into frame buffers.

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Reduced Logic for Boolean Operations on Raster Display Refresh Buffers

Raster graphics displays commonly employ a refresh buffer, a large RAM (random-access memory) storage comprising one or more frame buffers. Each frame buffer consists of a rectangular array of bitlists, one bitlist per separately illuminable point (pixel) on the display screen. These bitlists or lists of bits each represent a greyscale or color index, an index into a video lookup table. This article describes a mechanism whereby the hardware logic associated with changing the contents of frame buffers is reduced, saving card space (real- estate) and cost. This becomes particularly important in the case of a very high performance design which: (a) Provides the full set of sixteen boolean operators: Bitlist-NEW < -- Bitlist-OLD boolop Current-Color (b) Provides for flexible assignment of the RAM storage into frame buffers. For example, if the RAM storage consists of 'n' rectangles or planes of bits - each containing one bit per pixel - then subsystem microcode can configure the storage into between 1 and 'n' frame buffers, partitioning the set of planes in any way as long as each frame buffer comprises an integral number of bit planes. (c) Contains multiple "vector- to-raster" engines capable of operating in parallel on different frame buffers. These enable, for example, the simultaneous generation of side, rear and plan orthogonal projections from a 3D wireframe display list. From (a) above, it appears that each frame buffer needs its own Boolean operator register and needs the capability to perform all sixteen logical operations between the Current-Color and a chosen set of bitlists. The Current-Color is the color of the current graphic primitive being processed into the frame buffer. From (b) above, it is clear that the maximum number of frame buffers is the same as the number of bit planes in the refresh buffer. The hardware reduction which saves much of this logic consists of replacing the four-bit Boolean operator...