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Transparent Hardware Address Offset for Use in a Common Memory, Multi-Processor Environment

IP.com Disclosure Number: IPCOM000042346D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Livingston, DL: AUTHOR [+3]

Abstract

Using multiple processors in a computing system having a common memory array requires that provision be made for all processors to address the array. One manner in which this can be achieved is to assign a fixed starting address to the array. Each processor would then access a specific memory location using the same address. This technique requires that all processors included in the system have the block of addresses assigned to the memory array available for their use. This, however, may not always be the case. In instances where any or all of the processors are predefined computing systems themselves, that particular address block may already be dedicated to other uses.

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Transparent Hardware Address Offset for Use in a Common Memory, Multi- Processor Environment

Using multiple processors in a computing system having a common memory array requires that provision be made for all processors to address the array. One manner in which this can be achieved is to assign a fixed starting address to the array. Each processor would then access a specific memory location using the same address. This technique requires that all processors included in the system have the block of addresses assigned to the memory array available for their use. This, however, may not always be the case. In instances where any or all of the processors are predefined computing systems themselves, that particular address block may already be dedicated to other uses. A solution to this problem is to offset the address blocks for the various processors by means of a transparent hardware translation so that they can all access the same location in the storage array using different addresses. This is accomplished by first determining a base address for the memory and, next, choosing an address block for each processor of sufficient size to access the entire array. The interfaces for the individual processors to the common memory are then designed with the necessary address lines translated via hardware to perform either a subtraction or addition operation sufficient to offset the processors' address blocks to the memory base address. Implementing a transparent hardware...