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Fault-Tolerant Memory With Single Error Correcting Codes

IP.com Disclosure Number: IPCOM000042348D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Kaufman, D: AUTHOR

Abstract

A memory system, for example, a paging cache, includes a storage array 1 storing words including data bits and check bits under a non-saturated error correcting code about which more will be specified hereinafter. The input to the storage array 1 comprises a data path 2 including a true/complement gate 3 and a check bit path 4 including a check bit generator 5 and a true/complement gate 6. The output from the storage array 1 also comprises a data path 7 and a check bit path 8. Both paths 7 and 8 connect to a syndrome generator 9, the data path 7 connecting, in addition, to a true data correcting circuit 10 and a complement data correcting circuit 11. The output from the syndrome generator 9 connects to both correcting circuits 10 and 11 as well as to a syndrome decoder 12.

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Fault-Tolerant Memory With Single Error Correcting Codes

A memory system, for example, a paging cache, includes a storage array 1 storing words including data bits and check bits under a non-saturated error correcting code about which more will be specified hereinafter. The input to the storage array 1 comprises a data path 2 including a true/complement gate 3 and a check bit path 4 including a check bit generator 5 and a true/complement gate
6. The output from the storage array 1 also comprises a data path 7 and a check bit path 8. Both paths 7 and 8 connect to a syndrome generator 9, the data path 7 connecting, in addition, to a true data correcting circuit 10 and a complement data correcting circuit 11. The output from the syndrome generator 9 connects to both correcting circuits 10 and 11 as well as to a syndrome decoder 12. The outputs from the correcting circuits 10 and 11 connect to a multiplexer gate 13 capable of gating data in true or complement form and controlled by one of the outputs from the syndrome decoder 12. The remaining outputs from the syndrome decoder 12 control the correcting circuits 10 and 11 and provide system status signals, interalia controlling the cycling of the memory system. The signal outputs from the syndrome decoder 12 are shown as being of individual significance - true/complement (to the multiplexer gate 13), no error, single error, and multiple error - though other signals of compound significance could be substituted. The sequencing and timing controls are not shown. Assuming that the error correcting code used is one which will correct single errors and detect double errors, the basic writing sequence for one word is as follows: (i) write data bits together with the check bits generated therefrom by the generator 5 into a word location in the storage array 1 in true form; then (ii) read the data bits and the check bits so written and (a) if no errors are detected - END; or (b) if two or more errors are detected, rewrite the word, both check bits and data bits, in complement form into the word storage location from which it was read - END; or (c) if one error is detected, rewrite the word, both check bits storage locations from which it was read; then (iii) read the word just written and
(a) if no more than one error is detected - END; or (b) if two or mo...