Browse Prior Art Database

Processor to Processor Communication Method

IP.com Disclosure Number: IPCOM000042349D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Holland, HC: AUTHOR [+3]

Abstract

A communication method between master and slave microprocessors comprises the master microprocessor generating an address to a unique storage location of a shared memory device. The decoding of that address generates an interrupt to the slave microprocessor. As seen in the figures, master microprocessor (MMPR) 10 writes instructions into shared memory 11 via data bus 12, address bus 13, with a WRITE signal on command line 14. The instructions are then followed by count data on data bus 12 and a unique address reserved for the count data on address bus 13. The unique address is decoded by decode circuit 15 and a SET signal gated through AND circuit 16 by the WRITE signal from MMPR 10 on line 17 to the S input of latch 18.

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Processor to Processor Communication Method

A communication method between master and slave microprocessors comprises the master microprocessor generating an address to a unique storage location of a shared memory device. The decoding of that address generates an interrupt to the slave microprocessor. As seen in the figures, master microprocessor (MMPR) 10 writes instructions into shared memory 11 via data bus 12, address bus 13, with a WRITE signal on command line 14. The instructions are then followed by count data on data bus 12 and a unique address reserved for the count data on address bus 13. The unique address is decoded by decode circuit 15 and a SET signal gated through AND circuit 16 by the WRITE signal from MMPR 10 on line 17 to the S input of latch 18. In response to the SET signal, latch 18 generates an output on line 19 to send an interrupt request (IRQ) to slave microprocessor (SMPR) 20. MMPR 10 is now free to continue other operations, except communications with SMPR 20. The IRQ remains latched until SMPR 20 can respond. This SMPR 20 does by generating the unique address via address bus 21 with a READ command on line 22 to determine the number of instructions to be processed. The unique address on address bus 21 is decoded by decode circuit 15 and a RESET signal gated to the R input of latch 18 by the READ signal to AND circuit 23. Latch 18 in response to the RESET signal drops the IRQ on line 19. SMPR 20 thereafter loads the instructions in memor...