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Self-Tuning Notch Filter

IP.com Disclosure Number: IPCOM000042351D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Doran, SK: AUTHOR

Abstract

The combination of a switched capacitor notch filter and a phase-locked loop frequency multiplier automatically tunes the notch filter to reject single frequency noise. The circuit to be described is particularly useful for filtering out line frequency noise from an analog signal, as, for example, removing 50 or 60 Hz line noise from an ECG (electrocardiograph) signal. In Fig. 1, the noise-contaminated input signal enters at terminal 10, and the analog output freed of the noise signal appears at output terminal 14. The input signal is connected to the switched capacitor notch filter 12, an example of which is the MF10 Universal Monolithic Dual Switched Capacitor Filter manufactured by National Semiconductor Corporation [*], by means of resistors R1 through R4, as shown.

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Self-Tuning Notch Filter

The combination of a switched capacitor notch filter and a phase-locked loop frequency multiplier automatically tunes the notch filter to reject single frequency noise. The circuit to be described is particularly useful for filtering out line frequency noise from an analog signal, as, for example, removing 50 or 60 Hz line noise from an ECG (electrocardiograph) signal. In Fig. 1, the noise- contaminated input signal enters at terminal 10, and the analog output freed of the noise signal appears at output terminal 14. The input signal is connected to the switched capacitor notch filter 12, an example of which is the MF10 Universal Monolithic Dual Switched Capacitor Filter manufactured by National Semiconductor Corporation [*], by means of resistors R1 through R4, as shown. The frequency of the notch filter 12 is adjusted by the input line 16 which has a frequency of 100 times the line frequency. The multiple of the line frequency (noise) is produced by the phase-locked loop frequency multiplier 18, which receives a line frequency input on line 20 from comparator 22 and transformer 25 connected to utility power of a nominal 50 or 60 Hz. The output of comparator 22, a square wave of line frequency, is connected to one input of phase detector 24. The second input is derived from the divide-by-100 circuit 26 which divides the output of the voltage-controlled oscillator 28 by one hundred. Oscillator 28 is coupled to the output of phase detector...