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Simulating Pass Transistor Circuits Using Logic Simulation Machines

IP.com Disclosure Number: IPCOM000042354D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Barzilai, Z: AUTHOR [+4]

Abstract

The software simulation herein described permits logic design verification, fast turnaround for preliminary testing of new designs, and analysis of fault coverage characteristics of very large scale integrated MOS (metal oxide semiconductor) custom chips and systems. A network is mapped by assigning a data structure to each node and a number of logic processor instructions to each transistor. Each node is represented by a two-word record; three of the four bits in the record are used to represent the present node state, while the fourth simply reflects the current state (open, close) of the transistor for which this node represents the "source".

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Simulating Pass Transistor Circuits Using Logic Simulation Machines

The software simulation herein described permits logic design verification, fast turnaround for preliminary testing of new designs, and analysis of fault coverage characteristics of very large scale integrated MOS (metal oxide semiconductor) custom chips and systems. A network is mapped by assigning a data structure to each node and a number of logic processor instructions to each transistor. Each node is represented by a two-word record; three of the four bits in the record are used to represent the present node state, while the fourth simply reflects the current state (open, close) of the transistor for which this node represents the "source". As a result of the record format, only eight different node states are possible, which are chosen to represent the following physical states: H - "high impedance" state, representing a low capacitance node in the memory state. OM, 1M, XM - "zero", "one", and "unknown" states, respectively, representing a high capacitance node in the memory state. 1P - "one" state of a node connected to Vdd through a pull-up depletion-mode transistor. OI, 1I, XI - "zero", "one", and "unknown" states, respectively, of a node connected to either GND, Vdd or both inputs. The above states are arranged in the following priority structure:

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The four highest states are called "active" states, and the four lowest states are called "memory" states. The following assumptions are then made to differentiate between all possible physical circuit characteristics: 1. Switching transistors have either zero (when closed) or infinite (when open) resistance; depletion-mode transistors have a very large resistance compared to a conducting switching transistor. 2. No nodes ever become connected to ground through depletion-mode transistors; this saves the need for a Op state (in most cases, a OM state will accurately represent this condition). 3. Only two node capacitances are modelled, with the high capacitance significantly larger than the low one. These are assigned according to the physical circuit properties, except where a low capacitance node is intended to hold the state (memory). In this case, the node must not be connected to "real" high capacitance nodes (buses), and is given a "virtual" high capacitance status, thus enabling the simulation to record the node's state; where this is not possible, the function used to map the interaction between the high and virtual high nodes must give priority to the former over the latter. This scheme does not work for the case where a virtual high capacitance node may become connected to two or more real high capacitance nodes; in this case (and other similar ones), an extra instruction (or instructions, if n>4) is added which will set the state of the node in question to "H", if any of the relevant transistors is conducting, before the node updating phase

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is started (see below). Node st...