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Mechanism for Correcting Selected Double Errors Using a Single Error Correcting Code

IP.com Disclosure Number: IPCOM000042362D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Kaufman, D: AUTHOR

Abstract

One mechanism which will correct double errors, provided that at least one of the errors is a so-called "hard" error, while using a single error correcting code, comprises rewriting and rereading a word, initially deemed uncorrectable, in complement form. If the resultant syndrome indicates a correctable error (or no error), the complement can be corrected (or is already correct). However, the syndrome generated requires adjustment in respect of each check bit, if any, that is a function of an odd number of bits of the word which must, itself, be complemented before correction is performed. The adjustment is an invariant for a given code. The corrected complement word is again complemented to return the word to its required form or is complemented and then corrected.

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Mechanism for Correcting Selected Double Errors Using a Single Error Correcting Code

One mechanism which will correct double errors, provided that at least one of the errors is a so-called "hard" error, while using a single error correcting code, comprises rewriting and rereading a word, initially deemed uncorrectable, in complement form. If the resultant syndrome indicates a correctable error (or no error), the complement can be corrected (or is already correct). However, the syndrome generated requires adjustment in respect of each check bit, if any, that is a function of an odd number of bits of the word which must, itself, be complemented before correction is performed. The adjustment is an invariant for a given code. The corrected complement word is again complemented to return the word to its required form or is complemented and then corrected. The syndrome adjustment pattern is fixed for each specific code. One hardware configuration that will support the mechanism is illustrated in block form in the figure in which a conventional memory has added to it an adjuster 1, true/complement gates 2 , multiplexer 3 and path branches 4 and 12, as well as possibly, multiplexer 11 and branch path 5. The normal operation of the memory is to read a full word containing a data field and a check field from the storage array 6 into a syndrome generator 7 and to latch the data field in a correction circuit 8. The syndrome generated by the syndrome generator 7 is supplied to the correction circuit 8 and to an invalid syndrome detector 9 which will generate an uncorrectable error signal when an invalid syndrome is detected. If no such syndrome is detected, the data is passed to the data out path, unchanged or corrected, by the correction circuit 8. For writing, the data field passes directly to the array and to a check field generator 10 which generates the appropriate check field as the remaining input to the array required to complete the full word to be written. If the array 6 is so arranged that read-out is destructive, the data field output is fed back vi...