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Non-Complementary Clocked Differential Cascode Voltage Switch Logic

IP.com Disclosure Number: IPCOM000042379D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR

Abstract

The figure shows a two-clock differential cascode voltage switch (DCVS) circuit using only enhancement-mode devices. During standby time, phase-1 is on and therefore Q and Q' are both pre-charged high. It follows that all inputs (both true and complement) are also high and node A and node B are both low. Active time begins when phase-1 (D1) goes low and phase-2 (D2) goes high. Nodes A and B will remain low until the inputs reach a valid state by discharging one input line per pair to ground, at which time either node A or node B will go high and discharge one of the output lines. Load devices T1 and T2 are ratioed with the equivalent pull-down of the DCVS logic tree. A small amount of power will be dissipated during phase-2 time.

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Non-Complementary Clocked Differential Cascode Voltage Switch Logic

The figure shows a two-clock differential cascode voltage switch (DCVS) circuit using only enhancement-mode devices. During standby time, phase-1 is on and therefore Q and Q' are both pre-charged high. It follows that all inputs (both true and complement) are also high and node A and node B are both low. Active time begins when phase-1 (D1) goes low and phase-2 (D2) goes high. Nodes A and B will remain low until the inputs reach a valid state by discharging one input line per pair to ground, at which time either node A or node B will go high and discharge one of the output lines. Load devices T1 and T2 are ratioed with the equivalent pull-down of the DCVS logic tree. A small amount of power will be dissipated during phase-2 time. High performance is achieved due to the fact that the data propagation at the output is discharge limited, a favorable condition for an FET circuit. Standby current is essentially zero (except for leakage). Active current flowing through T1 and T2 (or one of them) is low, because T1 and T2 are small devices required to drive only small gate capacitances of T3 and T4. The charge-sharing problem does not exist and the input skew problem is eliminated because all inputs are high initially and there is only one type of I/O transition (discharge) involved during the active (or phase-2) time. Therefore, node A or node B will not move upward until the input condition is complet...