Browse Prior Art Database

Display Synchronizing Scheme

IP.com Disclosure Number: IPCOM000042398D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Hanson, CC: AUTHOR

Abstract

A typical CRT display system derives its sweep timing from a crystal oscillator. A clocking circuit driven from the oscillator provides timing pulses at the proper intervals to cause the display to scan the CRT in synchronization with the memory that stores the data to be displayed. In the system of Fig. 1, the crystal oscillator is replaced by a variable frequency oscillator (VFO) 10 whose frequency is controlled by synchronizing it to a pulse generated at the zero crossings of the power line. The 50 Hz signal 11 from the power line is compared to the vertical retrace pulse 12 from CRT display 13 in the phase detector. The control signal 14 generated by the phase detector 15 speeds up or slows down the VFO 10, and thereby clocking logic 16, until the vertical retrace 12 occurs exactly in sync with the 50 Hz power line.

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Display Synchronizing Scheme

A typical CRT display system derives its sweep timing from a crystal oscillator. A clocking circuit driven from the oscillator provides timing pulses at the proper intervals to cause the display to scan the CRT in synchronization with the memory that stores the data to be displayed. In the system of Fig. 1, the crystal oscillator is replaced by a variable frequency oscillator (VFO) 10 whose frequency is controlled by synchronizing it to a pulse generated at the zero crossings of the power line. The 50 Hz signal 11 from the power line is compared to the vertical retrace pulse 12 from CRT display 13 in the phase detector. The control signal 14 generated by the phase detector 15 speeds up or slows down the VFO 10, and thereby clocking logic 16, until the vertical retrace 12 occurs exactly in sync with the 50 Hz power line. When the display is to be operated from a 60 Hz line, it will be necessary to generate an alternate sync pulse. This can be done, as shown in Fig. 2, by dividing 60/6 in divider 17 and 50/5 in another divider 18, to generate two 10 Hz signals to lock together in phase detector 15. For commonly used phosphors, the refresh rate is usually close to 50 Hz. Near this frequency, the display will show disturbances ("flag waving") when operated in proximity to 50 Hz power supplies. It has been discovered that when the refresh rate is exactly the same as the power supply line frequency, these disturbances are reduced to an acce...