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Browse Prior Art Database

Testing of Personalized Embedded Arrays

IP.com Disclosure Number: IPCOM000042409D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Giuliani, SW: AUTHOR [+3]

Abstract

The creation of storage arrays having various personalized configurations from a basic master slice using VLSI techniques creates difficulties in testing and qualifying the personalized arrays. A separate test would normally be required for each of the personalized arrays. The figure depicts a method of providing a single test methodology for testing arrays, without regard to their configurations. The figure shows a method of providing a test which utilizes logic path evaluation techniques to evaluate the embedded array. Selection of different combinations of the AND-invert (AI) circuits provides the ability to provide delay evaluation by the path difference method. The following indicate various tests that can be performed: 1. Path 1 - Path 2 provides an inner macro gate delay. 2. Path 2 - Path 3 provides an array cell delay.

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Testing of Personalized Embedded Arrays

The creation of storage arrays having various personalized configurations from a basic master slice using VLSI techniques creates difficulties in testing and qualifying the personalized arrays. A separate test would normally be required for each of the personalized arrays. The figure depicts a method of providing a single test methodology for testing arrays, without regard to their configurations. The figure shows a method of providing a test which utilizes logic path evaluation techniques to evaluate the embedded array. Selection of different combinations of the AND-invert (AI) circuits provides the ability to provide delay evaluation by the path difference method. The following indicate various tests that can be performed: 1. Path 1 - Path 2 provides an inner macro gate delay. 2. Path 2 - Path 3 provides an array cell delay. 3. Path 3 - Path 4 provides a T/C (True/Complement) delay. 4. Path 1 - Path 4 provides an indication of total access time. Utilizing this technique, knowledge of the personalization of the array within the array boundary is not required to provide all of the meaningful tests required.

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