Browse Prior Art Database

High Speed Buffer With Dual Directories

IP.com Disclosure Number: IPCOM000042411D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Brandt, HR: AUTHOR [+2]

Abstract

This article describes a high speed buffer (cache) with fast access time for requests using logical addresses wherein a logical address directory is physically located close to cache data arrays while an absolute (or real) address directory, which may be conventional, is located further from the data arrays. It is desirable to make the cache size as large as the space available permits. However, the translation lookaside buffer (TLB) and cache directory usually become so large that they cannot be located close enough to the cache data arrays to achieve a fast (1 cycle) access time. This article describes compromise packaging in which two cache directories (address arrays) are used. In the figure, a first directory 11 is packaged close to the cache data arrays 14 and contains logical addresses in minimal size entries.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

High Speed Buffer With Dual Directories

This article describes a high speed buffer (cache) with fast access time for requests using logical addresses wherein a logical address directory is physically located close to cache data arrays while an absolute (or real) address directory, which may be conventional, is located further from the data arrays. It is desirable to make the cache size as large as the space available permits. However, the translation lookaside buffer (TLB) and cache directory usually become so large that they cannot be located close enough to the cache data arrays to achieve a fast (1 cycle) access time. This article describes compromise packaging in which two cache directories (address arrays) are used. In the figure, a first directory 11 is packaged close to the cache data arrays 14 and contains logical addresses in minimal size entries. A second directory 12 is packaged more distant from the cache data array and contains real or absolute addresses in its larger entries. The first directory is fast because it does not have to await the translation of a logical address to an absolute address in a TLB 16 before looking for a match in the directory 11. The two directories 11 and 12 are operated in parallel by a request from an instruction element (IE) being put into both a BAR (Buffer Address Register) 21 and a BCAR (Buffer Control Address Register) 22. If a request has a hit in the logical directory 11, the request is processed in about one machine cycle. The real directory 12 is also processing the same request and stores its result in the directory register 23. When logical directory 11 obtains a hit, the parallel operation by the real dir...