Browse Prior Art Database

Single Line, Multiple Timing Edge Transmission and Decoding Method

IP.com Disclosure Number: IPCOM000042414D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Gomez, RS: AUTHOR [+2]

Abstract

This article teaches a means of distributing and decoding additional timing edges in VLSI (very large-scale integration) test systems with minimum impact to system architecture. This allows expanded timing capability for complex, automatic test equipment, permits easy expansion of existing timing generation systems, and provides an extremely wide range of pulse possibilities with a minimum distribution system and a very small logic addition to each pin electronics card. BACKGROUND Major test systems use timing marks to start and stop latches on pin electronics cards and thus provide pulse capability for each card. The timing distribution layouts all use the concept of one marker per line for start and one marker per line for stop.

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Single Line, Multiple Timing Edge Transmission and Decoding Method

This article teaches a means of distributing and decoding additional timing edges in VLSI (very large-scale integration) test systems with minimum impact to system architecture. This allows expanded timing capability for complex, automatic test equipment, permits easy expansion of existing timing generation systems, and provides an extremely wide range of pulse possibilities with a minimum distribution system and a very small logic addition to each pin electronics card. BACKGROUND Major test systems use timing marks to start and stop latches on pin electronics cards and thus provide pulse capability for each card. The timing distribution layouts all use the concept of one marker per line for start and one marker per line for stop. The initial set of timing markers is a very significant consideration in a high speed system due to the fact that the distribution and offset can vary from timing line to timing line. This article teaches how to take maximum advantage of existing distribution and offset designs and allow for significant expansion of timing capability with a minimum impact to the system. It will also allow for split cycle, multiplexer (Mux)-mode testing without the loss of basic timing capability due to limitations in distribution capability. DESCRIPTION This description will be based on a system with four start and four stop markers distributed to the pin cards. Selection of start and stop markers is tied together so that selecting start 1 automatically selects stop 1. This is not a fundamental limitation, and the selection of start and stop markers could be independent. The start pulse sets a flip-flop that is reset by the stop pulse, resulting in an output to a timing logic AND gate. This method can produce one pulse waveform per phase, involving one start connection and one stop connection. The figure represents a modified pin card that allows multiple pulse possibilities per sta...