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Method of Determining the Performance Limits of a Device Under Test

IP.com Disclosure Number: IPCOM000042421D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Ward, HT: AUTHOR

Abstract

A method of testing a device under test (such as an integrated circuit (IC) chip), and of determining the performance limits thereof, is disclosed. The device under test receives parallel inputs at system data rates, the frequency gradually increasing until the outputs can no longer respond with correct results due to circuit delays through the device. According to the method described herein, the device outputs are fed back into the device inputs at a desired data rate. After many cycles, controlled by a counter, resulting in an equal number of pseudo-random input data patterns, the system is halted and the output "signature" is observed. The signature is then compared to a correct result which has been previously determined either by simulation or by another "good" test.

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Method of Determining the Performance Limits of a Device Under Test

A method of testing a device under test (such as an integrated circuit (IC) chip), and of determining the performance limits thereof, is disclosed. The device under test receives parallel inputs at system data rates, the frequency gradually increasing until the outputs can no longer respond with correct results due to circuit delays through the device. According to the method described herein, the device outputs are fed back into the device inputs at a desired data rate. After many cycles, controlled by a counter, resulting in an equal number of pseudo- random input data patterns, the system is halted and the output "signature" is observed. The signature is then compared to a correct result which has been previously determined either by simulation or by another "good" test. Any bad intermediate results not observed will be propagated to the final cycle. The figure illustrates how an integrated circuit is tested. The IC chip, a multiplier, may comprise two 28-bit operand registers, X and Y, which drive a 28 X 28 array of circuits that generate the full 56-bit output. Performance of the chip is determined by the time it takes operand data to ripple through the array to its final steady-state condition. Except for the input registers, the remaining logic (mostly array, drivers, checking circuits, etc.) is combinatorial. There are literally billions of combinations of data paths through the array. The time through the longest paths is representative of a worst-case performance. There are very many equivalently long paths, and it is desirable to exercise as many of these paths as is reasonably possible. In the figure, a switch is provided to allow "seed" values to be loaded into the X and Y registers from another data source. The clock signals, for loading these registers, are provided by external signal generators. Once loaded, the display is observed for the correct result. (An alternate way of loading "seed" values would be a serial input to the registers if designed as an LSSD...