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Driver Test SRL Circuit

IP.com Disclosure Number: IPCOM000042427D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR [+2]

Abstract

Fig. 1 depicts the implementation of a novel shift register latch (SRL) in series with an off-chip driver for enhancing VLSI chip testing by the level sensitive scan design (LSSD) technique. Fig. 2 is a block diagram of the schematic shown in Fig. 1. Block A1 comprises the combination of elements T1, T2 and R1. Block A2 is essentially T3 and R2. Block A3 is T4 and R3. Components T7, R12 and R13 provide the signal inversion and output dot. Block A4 comprises the T8, T9, R6, R7 and R8 combination. Block A5 is the combination of T5 and R4. Block A6 is the T6 and R5 combination. Elements T10, R9 and R10 provide the signal inversion and output dot. Finally, block A7 represents the combination of T11 and R11.

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Driver Test SRL Circuit

Fig. 1 depicts the implementation of a novel shift register latch (SRL) in series with an off-chip driver for enhancing VLSI chip testing by the level sensitive scan design (LSSD) technique. Fig. 2 is a block diagram of the schematic shown in Fig. 1. Block A1 comprises the combination of elements T1, T2 and R1. Block A2 is essentially T3 and R2. Block A3 is T4 and R3. Components T7, R12 and R13 provide the signal inversion and output dot. Block A4 comprises the T8, T9, R6, R7 and R8 combination. Block A5 is the combination of T5 and R4. Block A6 is the T6 and R5 combination. Elements T10, R9 and R10 provide the signal inversion and output dot. Finally, block A7 represents the combination of T11 and R11. Since the purpose of the SRL is to enhance testing, it is not critical that it demonstrate the same performance in relation to the clocks that a system useable SRL does. During normal system operation clock C is up and clocks A and B are down. In this state the effective block diagram of Fig. 2 will be as illustrated in Fig. 3. The effect of the delay of block A2 on the system performance is dependent on the wiring capacitance C1 which tends to have a wide range in the VLSI environment. Since by design block A2 has a low threshold and block A3 has a high threshold, when C1 is approximately 1 pf, the delay for a rising transition on C1 reaching the low and high thresholds of blocks A2 and A3, respectively, will be equivalent to that of a rel...