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Phoneme Buffer and Status Generator for Synthetic Speech Systems

IP.com Disclosure Number: IPCOM000042432D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Fasig, JL: AUTHOR

Abstract

A circuit using first-in, first-out (FIFO) buffers and a unique controller dramatically decreases the data transfer time in synthetic speech systems. Phoneme-based speech synthesizers typically require on the order of 70 bits of data per second for continuous speech output. Since most synthesizers have no capacity to store strings of phonemes, it becomes the responsibility of the controlling system to pass the phonemes to the synthesizer at the slow rate of 8-9 phonemes (bytes) per second. The consequence of this slow transfer rate is that in order to cause even a simple word or phrase to be spoken, the controlling system must spend a great deal of its time just waiting for the speech synthesizer to indicate its readiness to receive the next phoneme.

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Phoneme Buffer and Status Generator for Synthetic Speech Systems

A circuit using first-in, first-out (FIFO) buffers and a unique controller dramatically decreases the data transfer time in synthetic speech systems. Phoneme-based speech synthesizers typically require on the order of 70 bits of data per second for continuous speech output. Since most synthesizers have no capacity to store strings of phonemes, it becomes the responsibility of the controlling system to pass the phonemes to the synthesizer at the slow rate of 8- 9 phonemes (bytes) per second. The consequence of this slow transfer rate is that in order to cause even a simple word or phrase to be spoken, the controlling system must spend a great deal of its time just waiting for the speech synthesizer to indicate its readiness to receive the next phoneme. The present circuit relieves this problem by permitting the controlling system to transfer strings of up to 128 phonemes at a time at burst transfer rates of up to 1 million phonemes per second. A block diagram for this circuit (Fig. 1) includes FIFO buffer array 10 and FIFO controller 100. Phoneme data is transferred to 128-word by 8-bit FIFO array 10, and FIFO controller 100 then handles transferring that data from the FIFO array 10 to the speech synthesizer 200. The controlling system (not shown) presents 8-bits of phoneme and inflection data to the array 10 inputs. The array 10 (Fig. 2) signals its readiness to receive the data by making the READY FOR DATA signal high on line 15. When READY FOR DATA is high and the phoneme data is valid, the controlling system makes the DATA STROBE signal high on line 5 to transfer the data to the array 10. After 100 nanoseconds (minimum) the controlling system resets the DATA STROBE signal to the low state. Each phoneme in turn propagates through the FIFO 10 and collects in successive locations at the FIFO output where they cause the OR (output ready) signal on line 20 to go high. The timing for the phoneme data transfer is shown in Fig. 3. The FIFO controller 100 (Fig. 4) monitors the OR signal from the FIFO 10 as well as the -REQ (phoneme request) signal on line 205 (Fig. 7) from the speech synthesizer 200. The controller 100 delays the OR signal by at least 666 nanoseconds and latches this delayed signal ORQ in latch 110 to avoid basing decisions on transitory information. The -REQ signal is latched by latch 115 to generate the -REQQ signal. The reason for delaying the OR signal is to allow the phoneme data from the FIFO 10 to settle at the synthesizer inputs and satisfy the input data set-up time of that device. The FIFO controller 100 via AND circuit 116 then sets flip-flop 120 whereby the STB (strobe) signal on line 125 becomes high in response to +ORQ high and +REQQ. When STB goes high, data is simultaneously latched into the synthesizer 200 and shifted out of the FIFO 10. This causes the FIFO 10 to set OR low and also causes the controller 100 to set -REQQ high. When the de...