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Charge-Conserving Bit Line Boost Circuit

IP.com Disclosure Number: IPCOM000042434D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Streck, JP: AUTHOR

Abstract

This proposal modifies the design of a 5-volt bit line boost circuit so that 8.5 volts can be used selectively to excite the bit line on the high side of the circuit without having to pay for the power increase of approximately 2.9 times that otherwise would be required in going from a conventional 5-volt circuit design to a conventional 8.5-volt circuit design. This is accomplished by a charge-conserving arrangement whereby the trapped charge of approximately 5 volts from a previous boost operation is provided at the point in the bit line boost circuit where the voltage is to be boosted above 5 volts in the current operation, and the 8.

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Charge-Conserving Bit Line Boost Circuit

This proposal modifies the design of a 5-volt bit line boost circuit so that 8.5 volts can be used selectively to excite the bit line on the high side of the circuit without having to pay for the power increase of approximately 2.9 times that otherwise would be required in going from a conventional 5-volt circuit design to a conventional 8.5-volt circuit design. This is accomplished by a charge- conserving arrangement whereby the trapped charge of approximately 5 volts from a previous boost operation is provided at the point in the bit line boost circuit where the voltage is to be boosted above 5 volts in the current operation, and the
8.5-volt supply then is used merely to raise this trapped charge voltage by a desired increment to the higher voltage level, rather than having to furnish the full charge that would be needed in going directly from zero to that higher level. Fig. 1 shows the modified bit line boost circuit, which is designed basically as a 5-volt circuit but with special provisions for applying 8.5 volts at selected points therein, as will be explained. Associated with the complementary bit lines B/L and B/L' of this circuit are various capacitors and field-effect transistors whose reference characters are primed or unprimed according to whether these devices are associated with the bit line B/L' or B/L. Preferably these devices are of the double polysilicon type having oxide layers of two different thicknesses, 300 A and 450 A as follows: T1, T'1, T3: 450 A gate oxide; enhancement-mode device T2, T'2, T4, T'4: 300 A gate oxide; enhancement-mode device T'I/O: 450 A gate oxide; input-output device C1, C'1: 300 A oxide capacitors (inversion type) The thinner oxide layers in some of the devices listed above improve the operation of the circuitry by providing near-zero threshold voltages which facilitate the charge transfer functions performed by these devices. This feature, however, is not a necessary requirement for the successful use of the illustrated circuitry, and satisfactory results can be obtained with uniform oxide thicknesses if ease of manufacture is the principal criterion. Fig. 2 is a voltage-time diagram which shows the probable timing obtained with an on-chip timing chain. The cycle begins with the voltages 0D, 0H and 0bb at their up levels - 5.0 volts, 8.5 volts and 5.0 volts, respectively. In this initial state of the circuit, the bit lines B/L and B/L' and their respective nodes 1 and 1' are held at 5.0 volts through the devices T4 and T'4. Application of a chip select pulse to the chip starts the timing process, triggering 0D and 0H to fall. As the chip's timing proceeds, 0bb falls from 5 volts to approximately 2.5 volts, trapping the precharge of approximately 5 volts on nodes 1 and 1', inasmuch as T2 and T'2 are approximately zero- threshold devices. At 0 set time, the signal is amplified on the bit lines as in normal operation of a one-device memory cell, w...