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Arbitration on a High-Speed, Multiplexed Bus

IP.com Disclosure Number: IPCOM000042436D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Hinkel, SW: AUTHOR [+2]

Abstract

Arbitration logic for a high-speed byte multiplexed bus operates between two 1K-byte buffers and up to seven device logic components (DLCs). These DLCs are minimal function file attachments. Two file DLCs are allowed to do data transfer operations simultaneously, one to each buffer. They are also unbuffered and thus require transfer service every byte time. A 200-nanosecond transfer cycle requires a quick arbitration decision. The byte multiplexed characteristics require arbitration on each and every byte transferred. These unique characteristics, along with the normal design testability, cost and package constraints, require the arbitration implementation to be of a special nature. The arbitration logic includes four registers and corresponding control logic (Fig. 1).

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Arbitration on a High-Speed, Multiplexed Bus

Arbitration logic for a high-speed byte multiplexed bus operates between two 1K-byte buffers and up to seven device logic components (DLCs). These DLCs are minimal function file attachments. Two file DLCs are allowed to do data transfer operations simultaneously, one to each buffer. They are also unbuffered and thus require transfer service every byte time. A 200-nanosecond transfer cycle requires a quick arbitration decision. The byte multiplexed characteristics require arbitration on each and every byte transferred. These unique characteristics, along with the normal design testability, cost and package constraints, require the arbitration implementation to be of a special nature. The arbitration logic includes four registers and corresponding control logic (Fig. 1). The buffer cycle register 10 functions to store the DLC address assigned to one of the two available buffers. The request DMA register 40 latches the individual requests for data transfer from each DLC. The acknowledge DMA register 70 assigns the DLC its data transfer cycle. The grant buffer cycle register 100 assigns the buffer to its data transfer cycle. The control logic of decode buffer cycle block 150 decodes the DLC addresses assigned to each buffer. The logic in blocks 180 and 210 actually arbitrate cycles by allowing buffer 1 DLC requests to have priority over buffer 2 DLC requests. The logic of block 240 creates the strobe for the DLCs and the buffers to latch the data transferred. The timing chart in Fig. 2 contains most of the signals which are associated with the arbitration logic. Only two DLC request and acknowledge lines, DLC X and DLC Y, are listed because only two may be operating on a data transfer command simultaneously. Variables X and Y could represent any of the seven DLC signals on lines 31-37 inclusive in Fig. 1. The buffer 1 half of the buffer cycle register 10 is loaded with a DLC address from the internal data bus 5. The address is three bits associated with DLC X. When the signals BUF1 LOAD and LD BUF CYCLE REG on lines 11 and 12 are active and the L1 clock line 15 is pulsed, the address is loaded, as indicated by vertical line 1 in Fig. 2. The buffer 2 half of the same register is loaded with the DLC Y address in a similar manner (see line 2 in Fig. 2). The three-bit addresses, just loaded into register 10, must be decoded into seven signals for each buffer which will correspond with the eventual seven incoming DLC requests. This decode function is accomplished by logic in block 150. At any time following the address assignment (see vertical line 3 in Fig. 2) the DLCs will be instructed to operate upon a data transfer command (not shown). At some later time (see vertical line 4 in Fig. 2) the instructed DLCs will be ready to transfer data and consequently activate their DLC X REQ DMA and DLC Y REQ DMA signals. Both requests are activated simultaneousl...