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# Implementation of Monitor for Codes With Spectral Null

IP.com Disclosure Number: IPCOM000042441D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 28K

IBM

Todd, SJ: AUTHOR

## Abstract

This article describes the implementation of the monitor Finite State Machine (FSM) required for some channel codes with a frequency notch (see U.S. Patent 4,028,535). These codes are applicable to buried servo on magnetic disk files. Theory The FSM for a frequency null monitor has states , certain values of x and y. ( represents x+y*sqrt(-1).) It has two symbols, d= +1 and -1. For a frequency notch at notch times the bit frequency the transition rules are: (Image Omitted) The exact form of the function approx is not important: the closer approx is to rounding to the nearest integer, the better the frequency notch suppression will be. The present article discloses a simple implementation of the above equations.

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Implementation of Monitor for Codes With Spectral Null

This article describes the implementation of the monitor Finite State Machine (FSM) required for some channel codes with a frequency notch (see U.S. Patent 4,028,535). These codes are applicable to buried servo on magnetic disk files. Theory The FSM for a frequency null monitor has states <x,y>, certain values of x and y. (<x,y> represents x+y*sqrt(-1).) It has two symbols, d= +1 and -1. For a frequency notch at notch times the bit frequency the transition rules are:

(Image Omitted)

The exact form of the function approx is not important: the closer approx is to rounding to the nearest integer, the better the frequency notch suppression will be. The present article discloses a simple implementation of the above equations. If alpha is small, we may approximate sin(alpha)=alpha, cos(alpha)=1, so we approximate x' = d*( (x+d) + y*alpha ) = d*( x + y*alpha ) + 1 y' = d*( y - x*alpha ) We choose notch such that alpha is a negative power of two (say, we define logalph by alpha=2**-logalph). The follower may be implemented by bit selection and addition with no lookup or multiplication. We wire an x adder for (x + y*alpha) with the primary input wired to x and the secondary wired to y shifted logalph bits right. The bottom bits of y are lost, and the sign replicated in the top logalph bits. We wire the subtractor for y similarly. Hardware For a specific hardware example (see figure) we take a notch code where x and y...