Browse Prior Art Database

Universal Shifter

IP.com Disclosure Number: IPCOM000042442D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Barrett, S: AUTHOR

Abstract

Disclosed is a universal n-bit data shifter, including a pair of input multiplexers and an array of nxn IGFET devices. The shifter accepts data and shifts it in any amount in either direction depending on the control inputs. The functions performed by the shifter are: logical shift right (0 to n-1); logical shift left (1 to n); algebraic shift right (0 to n-1); rotate right (0 to n-1); and rotate left (1 to n). The n-input bits are initially selected by one or both of the input multiplexers under control of the function and select input signals. These input multiplexers provide all possible bit shift data patterns in a single dimension so that, by selecting n adjacent bit positions from the input multiplexers, the proper shifted output is derived.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Universal Shifter

Disclosed is a universal n-bit data shifter, including a pair of input multiplexers and an array of nxn IGFET devices. The shifter accepts data and shifts it in any amount in either direction depending on the control inputs. The functions performed by the shifter are: logical shift right (0 to n-1); logical shift left (1 to n); algebraic shift right (0 to n-1); rotate right (0 to n-1); and rotate left (1 to n). The n- input bits are initially selected by one or both of the input multiplexers under control of the function and select input signals. These input multiplexers provide all possible bit shift data patterns in a single dimension so that, by selecting n adjacent bit positions from the input multiplexers, the proper shifted output is derived. For example, for a logical shift left by k bits of n data bits, the n data bits are selected by the left input multiplexer (MUX) and zeros are selected by the right input multiplexer. Decoded shift inputs then activate the array of IGFET devices to gate bits k through n from the left multiplexer and bits 0 through k-1 from the right multiplexer to the n outputs in a single gating cycle. Logical shift right is accomplished in a similar manner by selecting zeros by the left multiplexer and data by the right multiplexer. Right and left rotate is accomplished by selecting data by both input multiplexers. Algebraic shift right is accomplished by selecting the significant or sign bit by the left input multiplexer and data by the right input multiplexer. Fig. 1 shows a 5-bit u...