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Browse Prior Art Database

Shared Instruction Address Register/Instruction Buffer Register

IP.com Disclosure Number: IPCOM000042446D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Brouillard, DA: AUTHOR [+3]

Abstract

An instruction buffer for improving performance in a computer system is a unique register intended strictly for the purpose of temporarily holding an extra instruction or instructions. In order to reduce hardware costs, a multiple-purpose register is provided to hold the extra instruction(s) in addition to providing some other function within the processor. This intermediate storage of an instruction is provided in a dual-purpose register while the first instruction of two simultaneously fetched or overlapped instructions is executed. The dual-purpose register is the Microinstruction Address Register (MAR) in the microprocessor local storage register (LSR) stack.

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Shared Instruction Address Register/Instruction Buffer Register

An instruction buffer for improving performance in a computer system is a unique register intended strictly for the purpose of temporarily holding an extra instruction or instructions. In order to reduce hardware costs, a multiple-purpose register is provided to hold the extra instruction(s) in addition to providing some other function within the processor. This intermediate storage of an instruction is provided in a dual-purpose register while the first instruction of two simultaneously fetched or overlapped instructions is executed. The dual-purpose register is the Microinstruction Address Register (MAR) in the microprocessor local storage register (LSR) stack. The result is achievement of a fast- instruction-fetch capability with minimal support logic and no negative performance impact compared to applications utilizing unique buffer registers. In fact, a performance gain is realizable when compared against configurations where the buffer register is provided external to the processor. The potential performance gain occurs in one-chip processors with the dual-purpose register being on-chip. In these cases, the instruction can usually be retrieved from the dual-purpose register more quickly than it can from an external register. Fig. 1 is a diagram of a dataflow for a one-chip microprocessor which executes instructions normally consisting of two bytes (16 bits) each. In reality, some instructions are of length greater than two bytes; however, since all instruction lengths are multiples of two bytes, each pair of bytes can be considered as an instruction. In the embodiment described herein, several dual-purpose registers are actually used to perform the buffering function. Which register specifically is used depends upon the current program level upon which the processor is operating. The processor of Fig. 1 has a number of program-operating levels,
(i.e., a main program level and six interrupt levels) which utilize the registers of a 64x16-bit LSR stack as general work registers and address registers. These registers are indicated in Fig. 1 and are shown in detail in Fig. 2. In Fig. 2, Registers 8 through 15 and 40 through 47 are the Microinstruction Address Registers (MARs) and Microinstruction Address Backup Registers (MABs) for the various program levels. The remainder of the registers form groups of general usage registers for associated program levels. The MARs are the registers utilized as dual-purpose registers. In the processor of Fig. 1, the Y-Register 8 functions as the current instruction address register for the active program level. Thus, whenever the processor changes program levels, the current contents of the Y-Register are moved to the LSR Stack MAR for the program level the processor is leaving. That is, the current instruction address for that program level is saved. The Y-Register 8 is then loaded with the starting address for the new program lev...