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Multiple-Line Signature Analysis Using Parallel Linear Feedback Shift Register

IP.com Disclosure Number: IPCOM000042447D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Fenton, BP: AUTHOR [+3]

Abstract

The use of a parallel linear feedback shift register enables the testing of logic circuit cards by signature analysis at functional speeds. Inputs to the shift register can be derived from multiple nodes in parallel, thereby reducing test time. The signature of the card, which is the remainder in the register after passage of the data streams from the nodes through the analyzer, is displayed as hexadecimal digits for comparison with the signature of a known good card. As the circuitry on cards has increased in complexity and density, it has become proportionately more difficult to test a card which is operating at functional speed. Digital circuits, especially those involving microprocessors, cause problems because of the large number of signals with long data streams.

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Multiple-Line Signature Analysis Using Parallel Linear Feedback Shift Register

The use of a parallel linear feedback shift register enables the testing of logic circuit cards by signature analysis at functional speeds. Inputs to the shift register can be derived from multiple nodes in parallel, thereby reducing test time. The signature of the card, which is the remainder in the register after passage of the data streams from the nodes through the analyzer, is displayed as hexadecimal digits for comparison with the signature of a known good card.

As the circuitry on cards has increased in complexity and density, it has become proportionately more difficult to test a card which is operating at functional speed. Digital circuits, especially those involving microprocessors, cause problems because of the large number of signals with long data streams. More traditional methods of testing these cards, such as stuck-fault testing, can lead to long test times and/or incomplete tests. These problems are magnified when both digital and analog circuits are combined on the same card. A solution which has become more and more popular in recent years is the use of signature analysis. This method is ideally suited for testing signals which consist of long, high- frequency data streams. Conventionally, signature analysis has been performed by feeding the signal into a serial linear feedback shift register (LFSR). To test a specified card operation, a signature is taken for each node of interest and then compared with the signatures taken from a known good card. The drawback of this test method is that a complex card with a large number of nodes to be checked will have a long test time. Using several signature analyzers simultaneously will reduce the test time but will require large amounts of hardware in the tester. Although it is possible to latch and then serialize synchronous parallel inputs from the multiple nodes and to apply the serialized bit stream to a linear feedback shift register for signature analysis, this has the drawback that the serializer and the LFSR will have to operate at a multiple of the card sampling rate. By using a parallel LFSR of the type described in U.S. Patent 3,703,705, which is much faster than a serial LFSR, the maximum frequency of the signals which can be tested is increased, permitting multinode testing of synchronous card operations at functional speed. In one particular application, the parallel LFSR is a Gallois field divider with a characteristic equation of: g (x) = 1 + x7 + x9 + x12 + x15 One suitable implementation of such a parallel LFSR is shown in Fig. 1. It has sixteen register stages x0 - x15 divided between two eight- bit clocked storage registers 10 and 11. Eight input...