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Multiple-Line Signature Analysis of Asynchronous Logic

IP.com Disclosure Number: IPCOM000042448D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Fenton, BP: AUTHOR [+2]

Abstract

A logic circuit card, which operates sequentially but asynchronously, is tested by the technique of signature analysis. The states of multiple test points on the card are captured in latches and loaded into shift registers. When any test point changes state, this is detected and the contents of these registers are clocked through a conventional signature analyzer to form a partial signature (remainder). This operation is repeated for every state change until the specific logic card operation under test has finished. At this point, the final signature in the analyzer is displayed and compared with a known correct signature. The system shown in the drawing receives inputs on a large number of asynchronous data lines 10. Each of these is connected by a probe to a test point on the logic card under test (not shown).

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Multiple-Line Signature Analysis of Asynchronous Logic

A logic circuit card, which operates sequentially but asynchronously, is tested by the technique of signature analysis. The states of multiple test points on the card are captured in latches and loaded into shift registers. When any test point changes state, this is detected and the contents of these registers are clocked through a conventional signature analyzer to form a partial signature (remainder). This operation is repeated for every state change until the specific logic card operation under test has finished. At this point, the final signature in the analyzer is displayed and compared with a known correct signature. The system shown in the drawing receives inputs on a large number of asynchronous data lines 10. Each of these is connected by a probe to a test point on the logic card under test (not shown). The lines are grouped, e.g., according to functional areas of the card. Data lines in each group are applied to set corresponding blocks of latches which are initially in a reset state. For simplicity, only two such latches 11 and 12 from two different blocks are shown. In practice, more than two blocks would be employed. The blocks of latches are, in turn, connected to corresponding shift registers, two of which are shown at 13 and 14. The latches may be addressed by means of a line address bus from a control processor to select only certain blocks or even individual latches for transfer of data to the shift register, depending on the function being tested and the test operation being performed. Transfer of the contents of the latches 11 and 12 to the shift registers 13 and 14 is triggered by a change of state on one of the input lines 10. This is detected by decoder 15 which produces a gate signal on line 16 to gate off the input to data latches 11 and 12 for the period required to sample the latches and signature analyze their contents. Another pulse output of the decoder 15 is applied on line 19 to reset a latch 20 whose output controls an oscillator circuit. The resetting of the latch 20 enables AND gate 22 to pass the output of an oscillator 23 to a counter 21 which was previously reset to zero by the set output of the latch. The output from the oscillator on line 24 clocks the contents of shift registers 13 and 14 via multiplexer 30 to a signature analyzer 31. The multiplexing function is controlled by a block address applied on bus 32 and initially operates to apply the...