Browse Prior Art Database

Delayed I/O Read/Write Circuit

IP.com Disclosure Number: IPCOM000042449D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Kummer, DA: AUTHOR [+2]

Abstract

In order to use an 8088 microprocessor with I/O devices designed for slower processors and to make use of negative edge-triggered devices, a circuit is provided for stabilizing the address and chip select signals faster and for making the data bus valid before the I/O write signal, by delaying both the I/O read and write signals. The circuit employs two J-K flip-flops to delay the read or write signal by synchronizing the negative edge with the system clock. An active (low) level on the processor's read (-RD) or write (-WR) line is applied through the associated inverter to remove the clear condition of the associated flip-flop. This allows the inverted output (Q of this flip-flop to go low on the next negative edge of the system clock.

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Delayed I/O Read/Write Circuit

In order to use an 8088 microprocessor with I/O devices designed for slower processors and to make use of negative edge-triggered devices, a circuit is provided for stabilizing the address and chip select signals faster and for making the data bus valid before the I/O write signal, by delaying both the I/O read and write signals. The circuit employs two J-K flip-flops to delay the read or write signal by synchronizing the negative edge with the system clock. An active (low) level on the processor's read (-RD) or write (-WR) line is applied through the associated inverter to remove the clear condition of the associated flip-flop. This allows the inverted output (Q of this flip-flop to go low on the next negative edge of the system clock. This signal is gated through the two-to-one multiplexer by the processor's IO/M signal to provide the delayed I/O read (-IOR) or I/O write (- IOW) signal. The positive edge of the -RD or -WR signal clears the flip-flop, allowing the delayed signals to return to their inactive (high) state without significant delay. Note, in the timing diagram, that the -IOR and -IOW signals are delayed by the period T2 and are now effective when the data bus AD7-0 has stabilized.

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