Browse Prior Art Database

Hi-Z Data in Buffer

IP.com Disclosure Number: IPCOM000042457D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Cordaro, W: AUTHOR [+4]

Abstract

The disclosed Data In Buffer provides the Hi-Z output state which allows the multiplexing of the Output Buffer and Data In Buffer on the same I/O, thus minimizing chip area and I/O pad requirements. The Data In Buffer is multiplexed on the same chip I/O pad with the output buffer. Consequently, this buffer is designed to have Hi-Z outputs (true and complement) under all conditions except a "Write Enable" operation. The buffer accepts TTL input levels and generates true and complement internal output voltage levels [0T(Vdd-Vt)] at the data in outputs IIO and IIO. The circuit, which uses Vdd=+8.5 V, also requires two voltage reference circuits for proper operation, a low voltage reference N N+1.

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Hi-Z Data in Buffer

The disclosed Data In Buffer provides the Hi-Z output state which allows the multiplexing of the Output Buffer and Data In Buffer on the same I/O, thus minimizing chip area and I/O pad requirements. The Data In Buffer is multiplexed on the same chip I/O pad with the output buffer. Consequently, this buffer is designed to have Hi-Z outputs (true and complement) under all conditions except a "Write Enable" operation. The buffer accepts TTL input levels and generates true and complement internal output voltage levels [0T(Vdd-Vt)] at the data in outputs IIO and IIO. The circuit, which uses Vdd=+8.5 V, also requires two voltage reference circuits for proper operation, a low voltage reference N N+1.5V, around which the input latch switches, and a high voltage reference, used in conjunction with transistors T20, T21, and T22, to either isolate nodes 5 and 6 from nodes 1 and 2, respectively, or to expose nodes 5 and 6 to nodes 1 and 2 during circuit operation. With the pre-charge clock, 0/pre, initially high (Vdd) (logical "1") and the address enable clock, 0/aen, initially low (logical "0"), which is the normal sequence for proper circuit operation, output latch nodes 5 and 6 are initially pre-charged to (Vdd-Vt) by devices T9 and T10. Thus, transistors T18 and T19 are biased "ON", and nodes 8 and 9 are at a logical "0" level. Devices T12, T13, and T20 are non-conductive at this time since node 7 is at a logical "0" level as a result of T7 being biased "ON" by 0/pre being initially at a high level. With nodes 8 and 9 at a logical "0" level, transistors T14, T15, T16, and T17 are "OFF" and outputs IIO and IIO are in a Hi-Z state. Also, with T20 being "OFF", transistors T21 and T22 are "OFF" and nodes 5 and 6 are isolated from input latch nodes 1 and 2. Input devices T26, T27, and T32 are biased "ON" and T29 is "OFF" when the precharge clock, 0/pre, is initially high, thus allowing the TTL signal to propagate to node 1. Transfer device T28 is also biased "ON", when 0/pre is high, forcing node 2 to the +1.5 V reference voltage. Any negative-going undershoots are clamped or attenuated by the combination of T26 and T29, device T29 turning "ON" only when the input voltage goes below ground. The input data is locked into latch node 1 when pre-charge clock 0/pre goes to a logical "0" level, turning "OFF" T26, T27, and T32. The 1.5 V reference is similarly locked into node 2, thus providing a voltage differential between latch nodes 1 and 2 equal to Input Voltage-1.5 V Ref . For a logical "1" input voltage level, for example, node 1 is at a higher potential than node 2. Therefore, as the enable clock, 0/aen rises after 0/pre falls, T25 turns "ON", allowing the input latch, consisting of T23 and T24, to set in a preferred state, which is further influenced by voltage coupling through capacitors C1 and C2 onto latch nodes 1 and 2 as the 0/aen clock rises. Because node 1 is initially setting at a higher potential than node 2, dev...